Posts by linpengcheng

Intel's plan to license x86 cores for chips with Arm, RISC-V and more inside

Intel plans to fulfill my prediction 8 months ago

2021-06-14, I published ["Prediction: Intel will use 'RISC-V plus x86 compatibility layer' or 'RISC-V plus x86 heterogeneous computing architecture' to develop a new generation of `warehouse/workshop model` CPU"](https://github.com/linpengcheng/PurefunctionPipelineDataflow/blob/master/doc/Intel_RISC_V.md).

I think Intel should use my solution, Because if Intel wants to implement this solution it has to use my "Warehouse/Shop Model", Because Intel's 10nm process is not as precise as the Apple M1's 5nm process, So it can't integrate as much memory as the Apple M1, ie: can't use the standard warehouse/shop model, can only use variant "dispatch center (virtual global unified warehouse, integration layer or platform, the parent company of the enterprise group)" model, and improve the shortcomings of not integrating large memory by increasing the cache.

Reference:

- 2022-02-14, Agam Shah, [Intel's plan to license x86 cores for chips with Arm, RISC-V and more inside](https://www.theregister.com/2022/02/14/intel_x86_licensing/)

- 2021-06-14, Lin Pengcheng, [Prediction: Intel will use "RISC-V plus x86 compatibility layer" or "RISC-V plus x86 heterogeneous computing architecture" to develop a new generation of "warehouse/workshop model" CPU](https://github.com/linpengcheng/PurefunctionPipelineDataflow/blob/master/doc/Intel_RISC_V.md)