* Posts by ee_engineer

1 publicly visible post • joined 19 Mar 2020

Xilinx's high-end Versal FPGA is like a designer handbag. If you need to ask the price, you probably can't afford it

ee_engineer

Re: This is Getting Ridiculous

Logic is hardened as a function reaches a tipping point. When most users need function X (e.g. DSP) it gets hardened as it is more efficient that building that function out of logic.

With this generation of technology there will be a range of families and parts with different ratios. E.g. Some will have the AI engines, some won't, so customers who need more/less DSP/LUT/Memory/AIE can choose the right part.

Parts are targeted for certain market segments.

>The thing is, taken to extremes, this trend will result in people using verilog / vhdl to marshall data in and out of these built in peripherals, and won't really do anything else with the data.

(1) The "built in peripherals" are not the same. The FPGA is massively parallel, with far more banwidth than a CPU (2) The Versal has a built in NOC which manages dataflow, so you don't have to use all your LUTs on interconnect as you suggest.

>Why wouldn't one skip the difficult, cumbersome vhdl / verilog part, and simply have a few lines of C running on a proper CPU marshalling data in / out of the same built in peripherals, achieving the same net result?

For your FPGA application, you would get nowhere near the same performance/power efficiency on FPGA vs cpu.

See example here:

https://www.linkedin.com/pulse/accelerating-decision-tree-based-predictive-analytics-winterstein/?trackingId=jRNvxSSnQt%2BHbbjOVXWabA%3D%3D

For one example, the performance is x764 vs CPU for the particular FPGA used.