* Posts by davidjapena

1 publicly visible post • joined 14 Aug 2018

Executing the DIMM sidestep: Movements in High Bandwidth Memory

davidjapena

Hi Chris, good article. I wanted to clarify your last remarks "If a supplier manages to develop a stacked DRAM DIMM then memory capacity generally could shoot up. However the expense of this could be so great that customers prefer to bulk out DRAM with 3D XPoint or some other SCMs that is more affordable than pure DRAM and still boosts host server performance substantially."

3D Xpoint won't be cheap any time soon. And most other emerging memories can only help with incremental improvement, and granted that can still be a welcomed reality. It would seem that a stacked DDR5 DIMM with 3DS components would provide less bandwidth, and more power/latency than HBM. So cost aside, its not clear that this would be ideal either.

Is the interposer higher manufacturing cost than stacking the DIMM?

Maybe 3DS RDIMM/LRDIMM would be better candidates over the above?

Maybe the manufacturing support and AI/DL/HPC demand will drive HBM cost down, and with its reduced footprint allowing for higher IC integration, maybe (the higher cost to target smaller node) DDR is more likely to be replaced by HBM?