Cache Coherency?
Chris Melnor – You wrote “It also appears that the SOCs contain a processor and its cores and also cache memory; so, if this is the case, we have a CPU using a memory hierarchy of cache, DRAM, local NVM and remote NVM – four tiers.”
That was, at first, my take as well. As suggested here, it is indeed only remote nonvolatile memory – not remote volatile memory - that can be accessed by another node’s processors. It happens, though that the scope of cache coherency is limited to individual nodes for both the volatile and nonvolatile memory accesses. So, yes, a Processor A’s cache (on a node M) can contain data from a remote Node N’s nonvolatile memory, but changes to that same memory by a Node X’s processors won’t be visible to software running on Node M.
Biting the hand that feeds IT
