At last, some RISC V Sanity
I think the article is a useful breath of fresh air.
RISC V has exactly one unfair competitive advantage - the hype surrounding it. Technically, it's yet another '80's RISC, perhaps with a bit more forethought given to instruction encodings, and without a delay slot. Ho-hum. Nothing wrong, but no unfair technical advantage whatsoever.
Recall that when it started, it was said to have been brought into existence to simplify the lives of computer architecture researchers. Prior to RISC V, such researchers had to cast about for an architecture which they could modify to explore and then show the fruit of their research. There really weren't many available - MIPS was an obvious choice because it was 'open', at least for a while.
But the problem for the researchers was that before they could get their brainchild to do useful work, they had to create an OS for it, and a compiler, and a library. And these had to be as good - more or less - as the existing ones for existing architectures. This meant that interesting research could spend only a small fraction of the research effort on the neat new stuff - they also had to do all this adaptation/redevelopment work on the software infrastructure.
The big thing that RISC V promised was that - if everybody based their research on RISC-V - then there were no architecture licensing issues - it was free and open as an architecture; and that the infrastructure work of compilers and OS and library etc would be done once, and everybody could share. Thus - higher quality research. And for that use, being "just a MIPS without a delay slot" was an advantage - adding neat new architecture to a vanilla old machine was just the playground one would like to show how much better your architecture improvements made things.
But now, folk are reckoning to get rich selling IP, or maybe SoCs, or maybe both based on designs with RISC-V cores inside them.
These products have no inherent advantage over (say) equivalent ARM-based products. Anything RISC-V in silicon will have exactly the same supply chain problems as an equivalent ARM-based SoC. Or a MIPS-based SoC. It's fab capacity that's in short supply. Not .pdfs
And there's nothing in the RISC V architecture which makes it better in silicon than an equivalent ARM. There's no magic.
So, yes; RISC V is a fine thing for academia. It's unencumbered. You can modify it if you insist. There's an OS port or two. llvm works. You can experiment using it in systems which choose to do things differently - where the fact that it's a RISC V is largely irrelevant, but having a free and unencumbered processor is highly convenient.
But for products? For profitable business?
As the article says, entirely unclear how RISC V leads to business success for RISCV IP and silicon vendors. Doesn't mean it won't or can't happen; just that its completely unclear.