Re: I would like to see a flat architecture 32 or 64 bit design.
"Test it with a FPGA evaluation board."
What gate clocking speed is achieved by 130nm? My Xilinx FPGA designs in 1986 ran with an external 100ns clock - the FPGA logic gates clocked somewhat faster. The 1800 gates required manual routing to be able to cram my design on one.
Given the number of gates on modern Xilinx FPGA chips plus module libraries - it feels like one would handle quite complex project designs. Baking in silicon as a first evaluation seems very retro and inefficient.