* Posts by Rupert Brauch

4 posts • joined 3 Jul 2007

IBM smacks rivals with 5.0GHz Power6 beast

Rupert Brauch

Performance claims

Hard to verify their performance claims of 2-3x the competition, since it doesn't look like they've submitted any benchmark results to www.spec.org

For all we know, they could be comparing their gear to ancient UltraSPARC III systems again.

Treehuggers lose legal fight to solar-powered neighbour

Rupert Brauch
IT Angle

Not a Redwood Forest

This is down the road from me, in Sunnyvale, i.e. Silicon Valley. This is not a redwood forest, it's a suburban area with roughly 5000 sq foot lots. It's inevitable that redwood trees would encroach on a neighbor eventually, since they grow to be so tall.

Angry investor offers to buy Transmeta

Rupert Brauch

@Hans Mustermann

"The fact is, all modern CPUs since the (IIRC) K5 already do code-morphing in silicon."

You mean like Itanium, POWER6, and almost all SPARC chips? Oh wait, those are all in-order native implementations.

There certainly are advantages to scheduling and optimizing in hardware. However, there are advantages to doing it in software, too. For example, software can consider a much larger instruction window, and can perform more radical transformations, since optimization need not take place concurrently with execution. These days, it's pretty cheap to have an idle (hardware) thread that can do optimization while the main program is running.

And software has been doing many of the things you claim impossible for years: speculative code motion, profile feedback based optimizations, and so on. There are even some run time systems that will detect that program behavior has changed over time, and reoptimize accordingly.

IBM hits software with 20 per cent Power6 tax hike

Rupert Brauch

re: Which proves x86 is better value

The number of instructions a chip can issue in a cycle is irrelevant. No general purpose CPU can sustain anywhere near its maximum issue rate, except in a very tight loop. It's impossible to predict the performance of a chip based on Instructions Per Cycle, number of threads or cores, or Mhz. The only way to make an intelligent decision is to measure it on a workload similar to the one you will be running.


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