Posts by Matt Reilly 1 4 publicly visible posts • joined 26 Aug 2009
As DH said, MIPS is in lots of things around you.
More importantly, the MIPS architecture is the foundation of
the indigenous microprocessor industry in the People's Republic of China.
That's a huge available market.
<check out the many recent stories about the PRC's MIPS
based netbook. The PRC wants a degree of independence from
the major x86 producers. MIPS is a rational choice for an ISA
given the comparatively simpler design challenges. >
The article explains the reasoning for the more expensive EX vs. the EP: they needed the extra QPI links to connect to the NUMA widget.
SGI isn't painting itself into any corners here with the EX: they're building an x86 shared memory machine on a scale that makes them unique in the market. The value of a true shared memory machine is compelling for a portion of the systems market. (That's pretty much why SGI was still shipping Itanium Altix. There are very few vendors (IBM, SGI, ?) offering SMP systems with more than a few dozen sockets.) The Nehalem EP would have limited them to one socket per NUMAlink chip. That may have been an unsuitable ratio of $ spent on processing vs. $ spent on the NUMAlink infrastructure. Balance is a big deal in these machines.
I wonder where the pricing will end up? Will they price just under the IBM umbrella and charge a premium? Or will they go after the top end of the cluster market?
First, a disclaimer -- I was a founder and Chief Engineer at SiCortex, but not intimately involved in either the management of the compiler group or the company at the time it was shut down (I left in January).
My understanding is that there are components that are not part of the compiler suite itself that were part of the Pathscale IP. These may have included things like compiler test infrastructure and other QA bits and pieces.
In general, this is very good news. The compiler will live on with a commercial sponsor (that was SiCortex' aim when the company bought the compiler team in the first place).
That's my understanding, as imperfect as it may be.
matt
SiCortex engineer -- July 2002 to January 2009.
Perhaps it was a typo, or perhaps it is a breakthrough. Both are possible. But if we're really talking offchip DDR bandwidth of 100GBytes/s from TWO DDR3 controllers, let's see what that would mean.
There may be 1600MHz DDR3 widgets out there. (1.6 G transfers per second.)
Each port contributes half the bandwidth, or 50GB/s. 50/1.6 is 32 bytes per transfer, more or less.
That means that each DDR3 port is 32 bytes wide. Hmmmm... That's something like 500+ pins devoted to offchip DRAM data path.
Quite within the realm of possibilities. Though one should note that "sustained bandwidth" is often far less than "maximum bandwidth". In this case, few DDR3 complexes get sustained bandwidth more than 70% of peak. (Take a look at the Nehalem stream triad scores.)
100GB/s is a good target. Achievable with heroic efforts. And the Power-X series has always been about heroic and extremely competent efforts. Please tell me it isn't a typo. ;)
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