Tim, power chips have never slipped their timeline
Tim, you may want to run a few searches on IBM power releases. I've worked for IBM since 1997 and we have NEVER slipped our timeline on Power chip releases. Every 3.5 years we release a new chip like clockwork. I don't know where you got the info that power 7 doesn't have a release date either. As usual it is slated for its 3.5 year iteration which is end of 2010. Power 6+ wasn't meant to be a speed increase. It was meant to increase capacity of existing servers as it is a quad core design vs. a dual core design for power 6. This increased capacity of our 16 way system to 32. The speed bump was just a byproduct.
This is straight from wikipedia
POWER3
Main article: POWER3
IBM introduced the POWER3 processor in 1998. It implemented the 64-bit POWER instruction set, including all of the optional instructions of the ISA (at the time), and had two floating-point units, three fixed-point units, and two load-store units. All subsequent POWER processors implemented the full 64-bit PowerPC and POWER instruction sets, so that there were no longer any IBM processors that implemented only POWER or only POWER2.
[edit] POWER4
Main article: POWER4
IBM introduced the POWER4 processor, the first in the GIGA-Series, in 2001. Like the POWER3, it was a full 64-bit processor, implementing the full 64-bit PowerPC instruction set; it also had the AS/400 extensions, and was used in both RS/6000 and AS/400 systems, replacing both POWER3 and the RS64 processors. There was a new ISA release at this point called the PowerPC 2.00 ISA, which added a couple of extensions to the ISA, such as a version of mfcr which also took a field argument.
[edit] POWER5
Main article: POWER5
POWER5 MCM with four processors and four 36 MB external L3 cache modules.
IBM introduced the POWER5 processor in 2004. It is a dual-core processor with support for simultaneous multithreading with two threads, so it implements 4 logical processors. Using the Virtual Vector Architecture, several POWER5 processors can act together as a single vector processor. The POWER5 added more instructions to the ISA.
The POWER5+ added even more instructions, bringing the ISA to version 2.02.
[edit] POWER6
Main article: POWER6
POWER6 was announced on May 21, 2007. It adds VMX to the POWER series. It also introduces the second generation of IBM ViVA, ViVA-2, which is the biggest change to the POWER series of processor since the transition from POWER3 to POWER4. It is a dual-core design, reaching 5.0 GHz at 65 nm. It has very advanced interchip communication technology. Its power consumption is nearly the same as the preceding POWER5, whilst offering doubled performance.
[edit] POWER7
Main article: POWER7
Currently in development at IBM, POWER7 will be the first of the Peta-Series. It's projected for release around 2010 and has been selected by DARPA as a potential processor to be used in their Peta-FLOPS SuperComputer. In the early 2000s, IBM submitted their proposal and received $53 million from DARPA to continue to participate in the challenge; in 2006, IBM received $244 million to build a petaFLOPS computer for DARPA.
Biting the hand that feeds IT
