Posts by Bruce Hoult

Chips that pass in the night: How risky is RISC-V to Arm, Intel and the others? Very

Re: Power ISA?

"Not to mention you can get entire desktops and servers with Power from Raptor Computing Systems. I can't recall seeing an equivalent for RISC-V."

Of course not. It's too new. It's not even five years since the RISC-V Foundation was set up and everything open-sourced. It's only a year and a half since the base instruction set, initial extensions (MAFDC), and privileged architecture were formally ratified and set in stone.

POWER has been going for thirty years.

RISC-V vendors have started with small embedded cores, with only a couple recently starting to get more into CPUs suitable for mobile applications processors let alone desktop or server. The most sophisticated RISC-V core so far -- SiFive's U-84 -- was announced at the end of October and the way these things progress will probably see first silicon around this time next year, and get into products six to twelve months later. The U-84 is competitive with ARM's Cortex A72 which was in the hot phones in 2016 and just found its way into the Raspberry Pi in June/July last year.

"For the 10 years it's been heralded as the saviour of open computing it's still very marginal, sadly."

That's what exponential growth looks like -- not worthy of notice for a long time, and then suddenly it's everywhere.

Look at the number of hospitals recently saying "we'll worry about coronavirus when we see a case" and then one or two weeks later they're "Our ICU is filled to overflowing and we're having to decide who we just let die, we're running out of beds with oxygen, 10% of our doctors have caught it and the rest are working 18 hour days and aren't allowed to see their families".

If you haven't noticed:

- Samsung has said the new Galaxy S20 has one RISC-V core controlling the camera and another controlling the 5G radio.

- Qualcomm has said every SoC they ship from now will have RISC-V in it somewhere.

- Espressif have said the new version of the ubiquitous ESP32 wifi/Bluetooth chip with main CPU core still Xtensa but an ultra low power RISC-V management core has gone to volume production.

- Microchip / MicroSemi has said the version of their avionics / military-qualified FPGA with embedded penta-core RISC-V FU540 is available to qualified customers for development now, available in volume Q3.

- Western Digital / Sandisk should be shipping their first disks and flash drives with RISC-V in them later this year.

It takes companies like these four or five years to go from "Hey, that looks interesting" to volume production. All those companies started working on RISC-V products years ago -- and it wasn't really available to people outside Berkeley until 2015 -- and you can be sure many many others have started the process in the last couple of years.

As for extensibility. The vast majority of custom instructions I've seen proposed don't affect the rest of the software in the system, don't even require changing compilers. These instructions are usually used in two or three places in a software library to speed up some specialized thing by a factor of five or twenty or whatever. Often it's not even worth modifying the assembler to know about them -- it woudl be easier overall to just encode them in hex with a .word directive where you need them.

But in fact the RISC-V GNU assembler has a special ".insn" directive that lets the user's program source define a new instruction using any of a number of standard instruction encoding formats and then immediately use it -- no modifications to the assembler.

For details see https://embarc.org/man-pages/as/RISC_002dV_002dFormats.html

That covers small, secret, extensions anyone can make.

Larger RISC-V extensions that will be standardized and made available for everyone go through a review process where experts from *many* companies and universities and research organisations look at them, try experimental implementations of them, suggest improvements etc. This process slows things down, but it's quite likely that the end result will be of *better* quality than any one company would do.

A little product renaming here, a little RISC-V magic there, some extra performance, and voila – Imagination's 10th-gen PowerVR is born

RISC-V management core

It's just the system management core, the same as Nvidia are doing, not the actual GPU cores like Think Silicon announced

https://think-silicon.com/2019/12/02/think-silicon-demonstrates-early-preview-of-industrys-first-risc-v-isa-based-3d-gpu-at-the-risc-v-summit/

Still, good to see, and there will be more and more things like this.

RISC-V business: Tech foundation moving to Switzerland because of geopolitical concerns

Re: Swiss Miss Incorporation

> I suggest people look into the deep financial benefits of incorporating in Switzerland.

> While the USA and U.K. have corporate tax rates of 35% and 28% respectively,

>Swiss land is 7.8%. Personal income taxes are very low.

It's a non-profit. There are no profits and therefore no taxes anywhere.

> RISC-V also has serious competition from open-source MIPS architectures which

> have code-size, performance, and existing market presence advantages compared

> to RISC-V.

Existing market presence,yes, I don't think there are a lot of high performance MIPS processors around by modern standards -- but I'd love to be educated. The code size thing is just rubbish. RISC-V has a big code size advantage over MIPS, except for the apparently stillborn NanoMIPS announced in May 2018 which has disappeared without trace.

Also MIPS Open has reportedly been quietly closed down already. I've confirmed that the signup page no longer exists and many others 404.

https://www.hackster.io/news/wave-computing-closes-its-mips-open-initiative-with-immediate-effect-zero-warning-e88b0df9acd0

Talk about a calculated RISC: If you think you can do a better job than Arm at designing CPUs, now's your chance

Re: "I did not know that ARM actually prohibited adding instructions"

Until now ARM absolutely did forbid licensees from altering the ISA in any way whatsoever. I believe the tagged pointer instructions were indeed added at the request of Apple, but you’ll find them documented in the ARMv8.4-A (I think) manual for all ARM licensees to use. ARM themselves haven’t shipped any CPUs implementing them, but then they also haven’t yet shipped any cores implementing SVE and that was announced and documented three years ago.

Re: Illegal instructions

Apple used illegal instructions to call system subroutines in the original MacOS, including many simple library things such as NewPtr() or opening and closing and reading disk files. Every M68000 instruction of the form 0xAnnn is an illegal instruction and Apple eventually used most of them.

Re: "I did not know that ARM actually prohibited adding instructions"

Er … on x86 instructions are up to 15 *bytes* not 15 bits. That’s 120 bits.

IBM hears the RISC-V kids partying next door, decides it will make its Power CPU ISA free, too

Re: Complements the RISC

RISC-V is not an implementation, it is an ISA.

The currently available implementations of RISC-V are low complexity, but you can be sure higher complexity higher performance implementations are in development at a number of companies -- most publicly at present Esperanto Technologies (who picked up Chris Celio of BOOM fame) and Alibaba.

Alibaba sketches world's 'fastest' 'open-source' RISC-V processor yet: 16 cores, 64-bit, 2.5GHz, 12nm, out-of-order exec

To pop this up a couple of levels for people who don't want to dig deep...

ONE VERSION of Linux runs on all RISC-V hardware. Hardware-specific patches are NOT needed.

All packaged Linux (etc) distributions can assume RV64GC. That is, 64 bit hardware including the extensions for multiply/divide, atomic transactions, single and double precision floating point, and variable length 16/32 bit instructions.

In any particular machine maintenance of caches or TLBs (for example) is either provided directly in the hardware, or else it is the responsibility of the hardware vendor to to provide Machine Mode software that traps and emulates the required functionality. This Machine Mode software must be installed by the boot process before the Linux kernel is invoked. As far as the Supervisor Mode software (e.g. the Linux kernel) is concerned everything Just Works.

The opcode is defined and programs (operating systems) can use it.

It's up to the chip designer whether the instruction is implemented in (as you point out) somewhat complex hardware that does everything OR traps to machine mode where a subroutine of normal instructions might have various logic, loops etc, that manipulate the TLB and/or caches of that particular core by reading and writing CSRs or possibly using some simpler custom instructions.

It's good for CPU designers to have a choice of how they do it, to cover a wide range of design points but with the exact same OS code running on all.

Similarly, the RISC-V architecture specifies the format of page tables in memory, but says NOTHING about what TLB hardware you might have, or whether TLB misses are handled with hardware that walks the page table or by a trap to Machine mode to do page table walking and TLB reload in software, or what.

Re: Right on the expected curve...

Thanks for your reply.

You're correct that the business model aspects of RISC-V are the important thing, not the technical merits or innovation, however it's definitely worth noting that the technical merits are right in the ballpark with things such as ARM or MIPS or SPARC, and better in some ways.

Yes, RISC-V makes a pretty good intermediate language or neutral software distribution format. It's very easy to emulate or JIT -- even the first working version of RISC-V QEMU immediately ran twice as fast as ARM32 or ARM64 versions of QEMU.

I was co-author of a RISC-V simulator and paper showing that if you concentrated on mapping directly to x86_64 you could get about twice the speed of QEMU, or often only about 20% to 30% slower than optimised x86_64 native code.

https://carrv.github.io/2017/papers/clark-rv8-carrv2017.pdf

Some other people have since picked up on this work and applied it to using RISC-V as a high performance method of implementing smart contracts on the Blockchain.

https://www.youtube.com/watch?v=wxZvX1GmvA4

You'll see my work referenced at around 17m15s.

I'm sorry but that's simply wrong. Look at the SFENCE.VMA instruction described on p114 of "The RISC-V Reader" or p56 of the reference manual:

https://content.riscv.org/wp-content/uploads/2017/05/riscv-privileged-v1.10.pdf

rs1 optionally specifies the VM page for which the mapping has been changed, and rs2 optionally specifies the address space in which the mapping has been changed. If neither of those is specified (i.e. is set to register x0) then the entire TLB needs to be flushed, but fine grained control is also possible.

Right on the expected curve...

RISC-V is coming from a standing start just a handful of years ago. CPUs such as the Western Digital SweRV and SiFive U74 are dual-issue in-order processors similar to the ARM Cortex A7 or A55 respectively or roughly like a Pentium MMX or PowerPC 603e but with more MHz (and 64 bit for the U74).

It's only a matter of time before many RISC-V companies have Out-of-Order CPU cores. CloudBear in Russia already announced their BI-671, Esperanto Technologies is going directly to OoO CPUs, the SHAKTI project in India are working on their "I Class". It would be surprising if others are not working on OoO cores as well -- especially those who already have dual-issue in-order working.

The Alibaba CPU is right where you'd expect it to be: pretty similar specs on paper to the ARM Cortex A75.

The performance numbers are .. right around what you'd hope you'd get by going to 3-issue OoO from the existing in-order processors.

Of course this is all nowhere near Ryzen or Skylake or Apple's much more aggressive than ARM's ARM designs. Give CPUs like that maybe five more years to start to appear in RISC-V land.

We've Falcon caught it! SpaceX finally nets a fairing half after a successful Heavy launch

Re: "the drone ship Of Course I Still Love You"

Since I’ve got the book in Kindle version … it’s from when the game player is trying to get back in touch with Contact, after refusing them.

“Well, I’ve sent the message to my friends, but—” He had a sudden, paranoid idea. He turned to Chamlis urgently. “These friends of yours are ships.” “Yes,” Chamlis said. “Both of them.” “What are they called?” “The Of Course I Still Love You and the Just Read the Instructions.” “They’re not warships?” “With names like that? They’re GCUs; what else?”

That’s it. If they’re mentioned elsewhere in Banks’ works I’m not aware of it. They’re certainly not in “Player”

Re: "the drone ship Of Course I Still Love You"

Hardly “characters”. Both are mentioned once in the same throw-away sentence, just to get a laugh it seems. They play no actual part in the (pretty darn good) story.

The Lance Arm-strong of performance-enhanced CPUs: Armv8.1-M arch jams vector math into super-microcontrollers

What happened to SVE?

It's interesting that this, MVE, is even necessary.

ARM's previous vector instruction set, SVE (for Scalable Vector Extensions), was announced in August 2016 and I believe is not yet shipping in any of ARM Ltd's cores yet, but only a Fujitsu ARM-based supercomputer processor).

And yet here we are with yet another vector processing instruction set announced.

Perhaps SVE didn't prove to be so scalable?

Meanwhile, the RISC-V Foundation's "Vector Extension Working Group" has been (frustratingly) slowly hammering out differences between microcontroller people and supercomputer people (and everyone in between) and since since earlier this month have a draft spec that probably several member companies will have available in silicon this year.

It looks as if the RISC-V V spec (with stable draft completed before anyone heard about MVE) scales to cover the whole ground covered by both MVE and SVE, as well as legacy SIMD ISAs such as NEON, AVX, SSE, MMX, while being very easy to use.

It's very interesting that in the MVE documents ARM talks about concepts such as executing vector instructions in beats, and chaining successive vector instructions together, because the RISC-V V spec is built with exactly the same (Cray-inspired) concepts in mind, as was the earlier "Hwacha" vector processor work at Berkeley six or eight years ago that RISC-V originally emerged out of.

Two out of five Silicon Valley techies complain Trump's H-1B crackdown has hit 'em hard

Re: H1-B abuse

I’m 56, have a job offer from a hot Silicon Valley startup for … well … a lot more than it costs to live there (not to mention of course more than the proposed future $130k minimum salary), and I’m waiting nine months and counting for them to even look at my application. Good thing I’m working for them as a remote contractor in the meantime, from wherever I want, which so far has included Moscow, Paihia NZ, Queensland Australia, and currently Fiji.

Linux lobby org joins with RISC-V bods to promote open chip spec

Re: There is Another Open Source CPU...

That would be an FAQ; https://riscv.org/faq/

Also: https://riscv.org/2014/10/why-not-build-on-openrisc/

OpenPOWER is not so open. I believe you have to pay substantial license fees to build a processor? Also, like MIPS and SPARC (and OpenRISC) the opcode encoding space is pretty much full, with little room for future standard or experimental extensions.

In RISC-V you can build a very simple CPU with fixed-length 32 bit opcodes and fewer than 50 instructions, taking very little space on an SoC or in an FPGA, and gcc and llvm will happily target that.

But at the same time, RISC-V supports instructions of any length from 16 bits to (at the moment) 176 bits (22 bytes) in multiples of 16 bits, with a standardised encoding that lets you know the length from looking at just the first 16 bits of the instruction. So you can do superscalar dispatch much more easily than for variable-length instruction sets such as x86.

I don't know of anyone using instructions of 48 bits or longer at the moment, but there is a standard extension that uses 16 bit opcodes to provide aliases for the most common 32 bit instructions, such as arithmetic where the destination register is the same as the first source register, or for loads and stores at small offsets from the stack pointer or another register, or for short program branches. This is course much the same idea as ARM Thumb or more recent MIPS and PowerPC features, but unlike the original Thumb doesn't require changing modes -- 16 bit and 32 bit (and longer) instructions can be freely mixed, as with Thumb2 or the new NanoMIPS.

Up in arms! Arm kills off its anti-RISC-V smear site after own staff revolt

Re: It bears repeating: Building a CPU that runs C fast considered harmful.

I find it amusing that my perfectly factual post ... and from someone helping design RISC-V CPUs and working on RISC-V compilers to run C fast ... got 30 downvotes here. Apparently a lot of people are half-educated. Oh well, lol etc.

Re: All publicity is good publicity.

RISC-V compilers are certainly newer and less optimised than ARM ones.

Despite this, SiFive's new E20 and E21 cores outperform ARM's Cortex-M0+ and Coptex-M4 on a Dhrystone MIPS/MHz and Coremarks/MHz basis, when both are compiled with gcc.

https://hackadaycom.files.wordpress.com/2018/06/coremarks.png

The ARM chips benchmark higher than the SiFive ones when using the IAD compiler. IAD has promised a beta of a RISC-V compiler for around the end of the year.

The RISC-V standard suggests that all but the very smallest RISC-V systems should include a "device tree" description of themselves in an onboard ROM.

The Raspberry Pi and other similar boards use obsolete SoCs that have already shipped in the millions in phones or other devices. For example the Odroid XU4 uses the same Samsung Exynos 5422 SoC as was in the Galaxy S5 phone. The Odroid C2 uses an Amlogic S905 SoC that was designed for set-top boxes. (I highly recommend both these boards over Raspberry Pi btw if you do want a high performance ARM board at a good price)

As RISC-V is new, it will be a while before there are obsolete SoCs that have already had their costs amortised in consumer products. What you have now in the Sifive HiFive1 ($59 320 MHz Arduino-compatable) and HiFive Unleashed ($999 quad core 1.5 GHz Linux board) are development boards aimed at professional engineers to evaluate the technology and prototype their software and products before they get their own hardware made. While $999 is expensive compared to a Pi or Odroid it's a drop in the bucket if you're paying an engineer $100k+ to work with it. Not to mention that the HiFive Unleashed has a lot of expensive stuff on it ... the 8 GB of DDR4 costs a lot more all by itself than the the Pi or Odroid (which have 1 or 2 GB of DDR3) retail for.

Re: It bears repeating: Building a CPU that runs C fast considered harmful.

Sadly you're not exactly correct there.

In the real world people who buy processors look at their performance on standard benchmarks such as SPEC or (horrors!) Dhrystone or CoreMark. These benchmarks are written in C. People who design processors therefore design them to run C as quickly as possible.

Certainly, the processor has no idea whether the instructions it is running originally came from C or Haskell, but if you were designing a processor mainly to run Haskell or Lisp or Prolog programs then the instructions might well look a bit different.

Companies tried building specialised processors for those languages (and others) in the 1980s, but the rate of improvement in conventional processors designed for C (or Pascal ... they're essentially identical at this level) was so fast that any improvement in efficiency was lost in lack of pure MHz.

Now that MHz has been stalled for a while, we may well start to see specialised processors -- or at least specialised instructions added to general purpose processors -- making a comeback.

'First ever' SHA-1 hash collision calculated. All it took were five clever brains... and 6,610 years of processor time

Re: 9,223,372,036,854,775,808 sha1 calculations

There are a total of 150 bits different, by the way.

Re: 9,223,372,036,854,775,808 sha1 calculations

They have published the two documents, I've downloaded them and confirmed their claims.

They are 422435 byte PDFs, differ in 62 of those bytes, have the same sha1 hash, and show different contents (the background colour). I haven't checked if there are any other differences in the display.

Apple Watch sales go over a cliff: Down 2.8 meellion per quarter in a year

couldn't buy one

I haven't worn a watch since I got my first GSM phone (Ericsson T10s) that showed the time in around 1999 or 2000.

But I went into half a dozen stores at the beginning of November trying to buy an iWatch and no one had the Series 2 for sale, only for display. I'll try again next week when I pass through Dubai airport.

You won't sell many if they're not actually available.

We're going to have to start making changes or the adults will do it for us

Of to argue about spaces vs tabs is to miss the point of the article. However…

I really don't care which, or how many spaces, or how wide tabs are. Just put a suitable description string in a comment in the file and Emacs (or one of the many editors that also understands it) will automagically put in the appropriate number of spaces or tabs or some combination thereof whenever you press the return key, or the tab key near the beginning of the line, or the semicolon at the end of the line.

Once that comment is there, I don't have to worry my silly little head about spaces or tabs again.

What should the Red Arrows' new aircraft be?

use a real fighter

The Red Arrows have always used a cheap trainer, which seems like a shame for such a populous, rich, and important country!

In my opinion even the RNZAF's A4 Skyhawks were a better display plane, let alone the RAAF's F/A-18s.

The USN Blue Angels now use the F/A-18, before that the A4, and before that the F4 (which the UK used to have a few of).

I think the F/A-18 (especially the F model) is the best display aircraft in the world right now, because:

- real fighter size and power

- not too expensive to purchase or run at $60m, vs $100m for Typhoon, and probably $40m for new Hawks.

- impressive high-alpha manoeuvres and very tight loops and turns

Here's my own shitty iPhone 4 video of an RAAF F/A-18 from a few years ago. Not being zoomed in too much (ahem) gives a good perspective on how small the display box is.

https://www.youtube.com/watch?v=6rPRAn9eGrg

I think the UK should bite the bullet and use the Typhoons. Would be impressive. And the UK can afford it.

Ghost of DEC Alpha is why Windows is rubbish at file compression

got his wires crossed somewhere

The article is ridiculous. The Alpha (even the original 21064) was perfectly good at bit-bashing and implementing any compression format you wanted.

Thanks to Anton Ertl, here are some timings of decompressing a 3 MB deflated file to 10 MB (i.e. gzip, zlib etc) using zcat:

0.351s 280m clocks 800MHz Alpha 21264B (EV68) 2001

0.258s 310m clocks 1200MHz ARM Cortex A9 (OMAP4) 2011

0.224s 240m clocks 1066MHz PPC7447A 2003

0.116s 230m clocls 2000MHz Opteron 246 2003

The fastest uses 25% fewer clock cycles than the slowest, and the slowest is not the Alpha.

Yes, the Alpha is the slowest in absolute time, but it's also the oldest and lowest clock speed. The Alpha was always considerably higher clock speed than its rivals made at the same time, at least until the Pentium 4 (which was high clock speed but not fast per clock).

What probably happened is Microsoft took some generic compression CODE (not format) that used byte reads and writes and simply re-compiled it for the Alpha, which didn't have byte instructions. It's not hard to rewrite the code to read 32 or 64 bits at a time and then use the (very good!) bit-banging instructions to split them into smaller parts. But that would take someone a week to do. You'd think Microsoft would have the skill and manpower to do that work, but apparently not.

The resulting code, by the way, would run faster on pretty much every other CPU too.

VW Dieselgate engineer sings like a canary: Entire design team was in on it – not just a few bad apples, allegedly

They couldn't —but they did

I don't get this "could not design a diesel engine that would meet the stricter US emissions standards" thing.

If it meets the standard in a particular software mode then … just leave it in that software mode all the time. Job done, you've designed an engine that meets the standards, no cheating.

So they CAN do it. Presumably that has some adverse affects, such as hurting drivability or power. But they can do it.

Tesla whacks guardrail in Montana, driver blames autopilot

> Is more than one car in 10,700 on the road a Tesla, or less? I don't know but my money is on "far less."

According to wikipedia: "An estimated 71,000 Model S cars have been sold in the United States through April 2016". Plus maybe another 5000 Model X. Call it 75000 total.

75000 * 10700 is just over 800 million.

Are there more than 800 million cars on the road in the USA, with population 320 million? No. It's about 260 million, including trucks and buses etc.

So, by that measure, Teslas are involved in 3x fewer accidents than the average vehicle.

I would bet that Teslas are driven at least an average amount of miles, and probably quite a bit more than average.

People don't know what "autopilot"s actually do.

"Autopilot" seems like a perfectly reasonable name for it to me. At least if you know what autopilots in normal small planes -- or even $50m ones -- actually do.

The autopilots found in virtually all aircraft will stupidly hold the altitude and direction you tell them, and will happily fly you straight into the side of a mountain or another aircraft.

Remember Germanwings Flight 9525? That was an Airbus A320, with one of the most sophisticated autopilots you'll find in a civilian aircraft. But tell it to fly at 100 ft and that's exactly what it will do.

Traditionally an autopilot's most fundamental task is keeping the plane level and relatively straight so the pilot can spend a few seconds or a minute or two reading the map.

Second is altitude hold. Simple ones just let you maintain the current altitude when you turn it on (same air pressure). More complex let you program a target altitude and will automatically climb or descend to it (but in small planes you have to watch the speed and adjust the throttle yourself).

Third is heading hold. Simple ones just maintain the current heading when you enable it. More complex let you move a "bug" on a kind of compass display to set a new heading. Historically, that's twin engine or small turboprop territory. More expensive still will automatically follow a path directly to or from a "VOR" or "ILS" radio beacon.

Fourth is speed control. Historically this is definitely only bigger planes. Otherwise you set the throttle yourself and you get whatever speed you get.

That's the historical state of the art, up until well under 20 years ago when GPS started to get approved for aircraft navigation. That lets you program in more complex and less restricted flight paths.

But it still knows nothing about mountains. At the most, some autopilots know about the Minimum Safe Altitude (MSA) in the current area -- that is an altitude 1000 ft above the highest point in a 25 mile radius.

As for avoiding other aircraft, the "TCAS" system was introduced around 1990 (but very rare then). This allows planes to pick up the radar transponder replies from other aircraft, determine where they are, and warn the pilot if there is a possible collision. This is now required for aircraft with more than 19 passengers, but in almost all cases it only gives a voice warning to the pilot who must still manually respond. It is also limited to telling the pilot to climb or descend to avoid the other aircraft, never to turn.

In 2013 Airbus announced the availability of retrofitting integration of TCAS with the autopilot across their range. The A380 (only) had the ability for a few years already. Given the reluctance of airlines to spend money, and the size of fleets, this will have made its way into only a tiny percentage of planes by now.

Linux letting go: 32-bit builds on the way out

Couple of facts about ARM...

Just want to mention a couple of things I noticed in comments:

-- the current standard Raspberry Pi model (Pi 3) is in fact 64 bit ARMv8 already. There is not yet OS support for 64 bits .. but that's kind of related to this article :-) I expect there will be soon enough. Of course there are still older models in service, and the Zero is not even ARMv7 (no Thumb2).

-- the armel vs armhf issue seems to have been decided for a while. All the common Linux distros seem to have already adopted armhf. Tizen is still armel. That's probably the most important one. Interestingly, armel vs armhf doesn't affect the kernel interface. No syscalls pass FP values directly as arguments, so the kernel is absolutely agnostic on this issue, and you can run both armel and armhf userland on the same kernel at the same time. I know this: I'm doing it every day to do armel dev on Pi and Odroid boards running armhf distros of Linux.

ARM Cortex-A73: How a top-end mobe CPU was designed from scratch

Re: How about an octal-core ARM based laptop/netbook?

The Pi3 is quite nice. I have one on my desk. But I also have an Odroid XU4, possibly the best bang for the buck in ARM boards.

The XU4 is $74 vs $35 for the Pi. But it's not actually twice the price, because you have to add at minimum an SD card to both, which is going to cost you a bit for a decent sized fast one. You also have to add a power supply to the Pi, which is probably going to set you back $20+. The XU4 comes with a 20 W power supply.

If you want a headless server to SSH into then you're done. Otherwise, add keyboard, mouse, monitor to both and the price difference starts to look trivial.

Once that's sorted out, the XU4 also has:

- about 2.5x the CPU power in each the main 4 cores (not even counting the LITTLE ones)

- 2 GB of fast DDR3 RAM vs 1 GB

- gig ethernet vs 100

- four or five times faster SD card interface (when used with a good card)

- PLUS an eMMC interface that is twice as fast as the SD card

- USB3 vs USB2

What's missing on the XU4?

- WIFI, Bluetooth, and 3.5mm sound out (but HDMI has sound)

The XU4 competes closely per core with a similar MHz core/core2. Think "White MacBook" of 2008 MacBook Air or something like that. But it's got twice as many (fast) cores.

Airbus to build plane that's even uglier than the A380

Re: @Bruce

"It's mainly Emirates that try to squeeze 3-4-3 into a 777, most carriers stick with 3-3-3."

That seems to be contradicted by ...

http://www.seatguru.com/airlines/Air_New_Zealand/Air_New_Zealand_Boeing_777-200_NL.php

... and ...

http://www.seatguru.com/airlines/Air_New_Zealand/Air_New_Zealand_Boeing_777-300.php

... both of which show 3-4-3 in Air NZ 777-200ER and 777-300 with 17.1 width and 32-33 pitch.

True, the older 777-200ER V1 shows 3-3-3, with 17.8 width. I don't believe any of those remain in service?

By contrast, Emirates A380 has 18.0 seat width in economy in 3-class config. For comparison A320/321 I've flown recently include Jetstar (17.8 or 17.9) and Aeroflot (18.0).

Love the A380

"carriers (well most of them) want to operate smaller aircraft more frequently. gone are the days of one flight per day to popular destinations"

I'm not so sure about that.

Here's a shot of the departures board in Auckland airport last Saturday while I was waiting to board EK413: https://pbs.twimg.com/media/Ci4oS5CUUAAOQU3.jpg

Not one, but three A380 flights departing from the same far-flung small city to Dubai within a 45 minute period, one each via Sydney, Melbourne, and Brisbane.

My flight was, I guess, about 90% - 95% full on both the Auckland to Sydney and Sydney to Dubai legs.

I don't dispute that the A380 is ugly, but there is nothing else that I'd be prepared to spend a total of about 18 hours in. The economy class seats are the biggest and most comfortable in the sky. The competitors (and alternative Emirates flights too) B777s have the most cramped seats in the sky -- Boeing designed it for 3-3-3 seating but the airlines forced them to squeeze in 3-4-3. As a result, 777 seating is WORSE than what you have in B737 or A320 for puddle jumper flights.

Note: I haven't yet encountered a B787. I believe the environmental conditions are similar to the A380 -- quieter, slower decompresion and recompression, and higher humidity than previous planes. I don't know about the seats.

What is money? A rabid free marketeer puts his foot in lots of notes

Re: cash is not the only money

WHY is very slow deflation -- at a rate matching the general increase in wealth and productivity -- a bad thing?

STUFF gets slowly cheaper. What's wrong with that?

cash is not the only money

I fear that Tim has got a bit confused about things such as gold and bitcoin.

They are not the only kind of money, they are only the cash. Both still allow the creation of money via entries in ledgers.

Tim is correct that as we get richer we need more cash -- or at least a greater *value* of cash. Both gold and bitcoin can increase in value arbitrarily so that even though there is a fixed amount of each, the value of that amount can increase.

For this to work, the cash has to be infinitely divisible, so that the smallest unit of cash can still buy one cheeseburger, not 1000 cheeseburgers as a minimum.

Gold is in theory infinitely divisible, but it could get a bit impractical when you need an electron microscope to count your cash to buy a cheeseburger.

Bitcoin is in actual fact infinitely and conveniently divisible.

Note: the Satoshi is 1/100,000,000th of a bitcoin, and is currently the smallest unit. That in itself will last us a very very long time of expansion of the value of bitcoins before it become a problem. But if it ever does become a problem, all that is needed to fix it is a simple software update of the bitcoin protocol.

As we all know, snark always comes before a fall. Mea culpa

and applied to person electronics manufacturers...

... this could be one reason that Apple does so well since St Jobs came along and axed dozens of indistinguishable models of computer and replaced them with the 4-way desktop/laptop vs consumer/pro matrix of models. (plus choice of RAM and disk sizes within each model)

They've continued this with iPods, iPhones and iPads. There are currently five models of iPhone (5s, 6, 6+, 6s, 6s+) and five of iPad.

I don't even know where to start when someone asks me to help them decide on a Windows computer or Android phone. And I'm a computer processional working on the guts of Android (the Java compiler/runtime) for a major Android phone manufacturer!

Perhaps middle-aged blokes SHOULDN'T try 34-hour-long road trips

Re: NZ and territories

Yes, in NZ all lanes are legally equal, and in some way separate roads. It is regarded as polite for slow traffic to keep left, but I don't think it's enforceable.

I once got pinged for using a motorway onramp to overtake, there being three vehicles driving persistently side by side in the three lanes for some km. My offence, apparently, was changing lane from a proper motorway lane onto the onramp -- not the overtaking itself.

NZ and territories

In fact Samoa, (formerly a NZ territory and still very closely linked), changed from driving on the right to driving on the left on 8 September 2009. They also by the way changed time zones by 24 hours in December 2011, to be in the same day and NZ & Australia instead of nearly a day behind like Hawaii (and American Samoa).

In NZ there are distinct "passing panes" in which the fast traffic merges with the slow, and "slow vehicle bays" in which the slow traffic merges with the fast.

The problem with slow vehicle bays is that no one driving a car ever thinks of themselves as "slow" (trucks are better about this), so I very often end up overtaking two or three cars on the left side, using the slow vehicle bay.

New Tizen phone leaked: Remember it's not all just Android and iOS

Re: get the units right

Excuse me while I take a Sharpie to every AA NiMH cell I've ever owned...

sheesh

$30 Landfill Android mobes are proof that capitalism ROCKS

history repeats

Do you know what you sound like? I'm reminded *so* much of those MS-DOS die hards when Windows 95 was already out.

Early Android was pretty much crap, but even an iPhone fanatic has to admit that Lollipop and even Kitkat aren't terrible. There's no real reason to switch from iOS to Android (or Mac to Windows) but for those without an investment in apps and accessories there isn't a lot of downside either.

Recent Windows phone too.

But anything pre-iPhone is positively primitive. We've got the cheap computing power now, there's no reason not to use it. The better phones now have more computing power than Mac and Windows laptops had when the iPhone came out.

What a hang-up: AT&T dumped from Dow index, Apple installed

the Dow is dumb

Eddy, yes and that is exactly why the Dow should be ignored. Price weighting makes no sense whatsoever. Market cap weighting is the only meaningful way to make an index. Ridiculous that a stock having a split should change their contribution to the index, or move the index at all.

And the buggiest OS provider award goes to ... APPLE?

not consistent at all

This is pretty silly. Most of the bugs found on OS X were in SSL, bash and so forth that are present on Linux as well, just not in the *kernel*.

Bitcoin trade biz MyCoin goes dark, investors fear $387 MEEELLION lost

how is this bitcoin related?

Is there any evidence that this shonky outfit actually invested people's funds in anything, let alone in bitcoins? It sounds like it's just a pure con for the greedy.

The reporting seems very unclear to me whether people paid in dollars, or bitcoins, or what.

HK$400,000 is about US$50k. If that is promised to pay out 90 bitcoins, that's only about US$20k at the moment, though it was up to $90k at this time last year.

Uber isn't limited by the taxi market: It's limited by the Electronic Thumb market

Not really, and for two reasons

The first is that the only resource from the Earth we're actually using up is energy. And the actual atoms still exists even after we've thrown things away.

Eventually, our garbage dumps will become the highest concentration sources of iron, copper etc and we'll start mining them.

The other reason in that the multiplier between physical resources used and economic value can be as close to infinite as you can imagine.

Suppose a comedian stands up on a stage for an hour, and then sells the recording to 100 million people as an internet download for $10 each. That's a billion dollars of value created from the expenditure of how many resources? A Big Mac, pretty much.

SpaceX makes nice with U.S. Air Force, gets shot at black ops launches

of course?

What on earth is this "of course"?

SpaceX already has massively lower costs than ULA even if they throw away every Falcon 9 after use, just like ULA does.

If/when they do manage to reuse engines or stages, that will drop their costs massively again.

But they don't *need* it. Let alone "of course".

Scientific consensus that 2014 was record hottest year? No

Re: The stupid. It BURNS.

Interesting the amount of ad hominem against Mr Page. An argument equally as invalid as "consensus".

Re: What is it with the registers coverage of global warming.

No, that's not really the case. Even under the most extreme predictions, it is vastly cheaper to adapt to changes in climate than to try to make deliberate adjustments to the climate of the whole world.

Re: Cut the sh*t!

I would place a reasonable sporting bet that it will be cooler in 2030 than it is now ... maybe not as cool as 1990, but maybe 1995.

I should get pretty good odds on that, right?

SpaceX drone hovership ROCKET LANDER BURN: Musk to try again

not sure it'll be tried on the next launch

Have SpaceX actually said they'll attempt a landing with the Deep Space Climate Observatory launch?

A landing attempt means keeping fuel in reserve, and not using it for the primary mission, which subtracts from the available launch performance.

Geosynchronous or interplanetary launches normally require the full Falcon 9 performance capability.

ISS and other low earth orbit launches don't require maximum performance, and that's when they've been trying the flyback experiments.