> No, RISC-V is nowhere near as fast as Arm; yes, lots of people regularly claim it is,
No sane person could claim that currently shipping RISC0V is as fast as currently-shipping Arm. It's just not even close.
Take my own primes benchmark [1], for example. The fastest RISC-V right now is the Milk-V Pioneer, at 9.622 seconds (EIC7700 is a couple of seconds slower, btw). AWS Graviton4 c8g does it in 3.075 seconds, over 3x faster.
> or will be within months
Not months, but a couple of years, yes. Announced -- that is design completed and tested in simulation -- RISC-V designs are out comparable to recent Arm designs e.g. SiFIve P870 vs Cortex X.
> or that the differences are trivial.
The ISA differences are trivial, and RISC-V and Arm implementations with similar µarch have comparable speeds e.g. SiFive U74 is very comparable to Arm A55, better than Arm A53 etc.
> Perhaps there is a strict, precise technical definition of this term that I don't know.
Yes. An Instruction Set Architecture is an Instruction Set (that is, literally, a set of instructions that a computer can run, enabling one to write programs using those instructions) that is an Architecture enabling and containing multiple different implementations with different speeds and prices but which run the same programs. The term originated in 1964 when IBM announced on the same day multiple different IBM S/360 machines that all ran the same program binaries, but varied in price and performance by a factor of more than 50x.
x86_64 is an ISA. Ice Lake and Zen 2 are implementations.
Wirth RISC is an ISA, RISC-5 is an implementation -- in fact RISC-4 and RISC-5 are the same CPU implementation as RISC-3 but just with added peripherals: an SPI SD card interface in RISC-4 and PS/2 keyboard and mouse, VGA display, and network (via SPI) in RISC-5.
> For me, that counts as predating RISC-V; YMMV.
You published your article in December 2015, Wirth published his paper in September 2015. I have no idea when Wirth started using the names RISC-0 to RISC-5 himself, but I can't find any earlier publication about it.
The first publication of the name "RISC-V" was possibly “The RISC-V Instruction Set Manual, Volume I: Base User-Level ISA” in May 2011 though the ISA underwent some evolution between then and the compatible with today's chips user-mode spec in May 2014:
https://www2.eecs.berkeley.edu/Pubs/TechRpts/2011/EECS-2011-62.pdf
https://www2.eecs.berkeley.edu/Pubs/TechRpts/2014/EECS-2014-54.pdf
The first commercial RISC-V hardware (a 320 MHz Arduino Uno compatible board) was shipped in December 2016 and I had one in my hands in Moscow the next month. Wirth of course never shipped any real RISC-5 chip, but only an FPGA implementation (in 2015). The RISC-V Rocket core was published and publicly available for anyone to run in FPGA in 2012, and Berkeley of course made a number of test chips for internal use too.
The first public RISC-‐V Workshop was held in Monterey, CA on January 14, 2015 and the second at Berkeley in June 2015. Even before that, the RISC-V team made a splash at the Hot Chips conference in August 2014.
https://riscv.org/announcements/2014/08/risc-v-at-hotchips-26/
So there was a LOT of public RISC-V activity before Wirth published his paper or you wrote your article.
The Oberon language and OS of course dates from the 1980s, and I was using it on a Mac back then. There was hardware at ETH in the early 80s but it was built around the commercial NS32032 CISC microprocessor.
[1] http://hoult.org/primes.txt