Posts by Bruce Hoult

Intel's latest CEO Lip Bu Tan: 'You deserve better'

" while I can get 128 GB of RAM into a desktop if I pay enough, getting 128 GB of VRAM is not very likely"

Ahh, but you're wrong.

Mac Studio: Apple M3 Ultra chip with 32-core CPU, 80‑core GPU, 32-core Neural Engine, 512 GB unified RAM: $9499

Or if you only want a paltry 128 GB RAM then $3499 with the Apple M4 Max chip with 16‑core CPU, 40‑core GPU, 16‑core Neural Engine.

Or $3999 if you step up to the 28-core CPU, 60-core GPU, 32-core Neural Engine. That one can also have 256 GB RAM.

That RAM is in the physical CPU package, and fully usable by the GPU as well as the CPU.

Even MacBook Pro laptop can do 128 GB unified RAM with M4 Max chip with 16‑core CPU, 40‑core GPU, 16‑core Neural Engine, either 14" or 16", though at high price than the Mac Studio.

Chimera Linux ghosts RISC-V because there's no time for sluggish hardware

As it turns out, they've persisted, done a build on the Pioneer, and RISC-V is not being dropped.

https://chimera-linux.org/news/2025/03/new-riscv-server.html

Well done!

Re: Yup

> Also, for good measure, it can be worth mentioning that both AArch64 and RISC-V were introduced in 2011, with one now successful everywhere (from smartphones to supercomputers) and the other, not quite.

No, that is absolutely incorrect and misleading.

In October 2011 Arm unexpectedly published the complete, comprehensive Aarch64 instruction set manual, and 12 months later the A53 (in-order) and A57 (OoO) cores.

They will have been working on designing Aarch64, in secret, for many years beforehand. I don't think Arm has ever said exactly when they started, but it's surely at least five years earlier, and quite possibly around the time AMD announced (April 1999) or maybe more likely shipped (April 2003) amd64 and it became apparent that the 64 bit future was not going to be dominated by Itanium.

In contrast what happened with RISC-V in 2010 was that three academics at Berkeley got the idea to START designing a new ISA. It was worked on at fairly low effort for a number of years, really starting to kick off finalising the ISA in around 2015 when the first public meeting was held, the RISC-V Foundation was formed, and SiFive was founded. At that stage the basic RV64GC User-level ISA was fairly stable, but the privileged architecture for S mode etc was not completed until 2018.

The RISC-V equivalent to ARMv8.0-A being published in 2011 is probably the ratification of the RVA22 profile in December 2022, or possibly when most of its component ISA extensions were ratified in December 2021. Cerainly no earlier than the initial base ISA ratification in July 2019.

Any claim that Aarch64 and RISC-V had equivalent status in 2011 is simply ludicrous. Arm had at least an eight year head start, if not eleven. If Arm started work, at some level, in 2000, soon after the announcment of amd64 then the 11 years from then until publication of ARMv8.0-A is basically identical to the time from RISC-V being started to the ratification of RVA22.

> It is a disappointment so far,

Only for bystanders who don't understand the above.

RISC-V development has been done in the open, cooperatively by people from many companies and academic institutions. Aarch64 was developed in secret and then announced, fully-formed.

Re: usable if you're patient

It's all relative, innit? What is being described as too slow here, HiFive Unmatched, is effectively like a 1500 MHz quad core original Pentium (maybe more like Pentium MMX) with 16 GB RAM. It's comparable in overall performance to somewhere in the Core 2 Duo run during the late 2000s.

Re: Yup

> a tad slower than A72", which is 10 years old, and found in the Raspberry Pi 4 nearly 6 years ago.

A72 was announced in February 2015 and the P550 in June 2021, 6 1/4 years apart.

The Pi 4 shipped in July 2019, 4 1/2 years after the A72 was announced.

The HiFive Premier and Milk-V Megrez shipping in January 2025 is just 3 1/2 years after the P550 was announced ... nine months faster than the A72 took to the Pi 4.

It would have been 2 1/2 years if Intel had followed through on mass-producing Horse Creek, also with P550 cores, in early 2024. They showed a running machine at a conference in September 2023. It was good that Eswin was able to step in so quickly, though the chances are high that Intel's chip would have been higher performance.

RISC-V is new. Very very new. The very first RISC-V chip, the FE310 microcontroller, was available in very limited quantities (just a few hundred) on the HiFive1 in January 2017 -- that's two years after the A72 was announced -- and the ISA with S mode needed to run OSes such as Linux was published in the same month that the Pi 4 shipped in 2019.

RISC-V started when Arm was already mature, but the rate of progress is as fast or faster.

Re: Yup

An ISA is not performant or non-performant. Particular hardware examples are.

Most of the currently-shipping RISC-V hardware is dual-issue in-order running at 1.5 to 1.8 GHz. Similar µarch and similar clock speeds and similar performance to Arm A53 and A55 boards, and a tad slower than A72.

Faster cores and SoCs are coming -- and the twice faster EIC7700 SoC just started shipping on two different boards earlier this year -- but the main thing in available hardware in the last couple of years has been decreasing prices at the same performance level. In 2021 the HiFive Unmatched cost $665, while just yesterday I took delivery of a very similar performance (but newer ISA with RVA22 and Vector) Orange Pi RV2 with 8 GB RAM for $49.90. A farm of those would be great for building an OS's packages.

https://aliexpress.us/item/1005008612193589.html

I haven't had a chance to test it yet, but the Lichee Pi 3A with the same CPU cores builds a RISC-V kernel in 70m57s while an M1 Mac Mini running RISC_V Ubuntu in docker takes 69m16s -- basically identical, but the Orange Pi is many times cheaper.

With what is currently in the pipeline the next couple of years are going to see a rapid advance in per-core performance on RISC-V, catching up to Arm around 2027/8.

Lots of packages can't easily be cross compiled. Things are much easier doing a "native" build, either on real hardware or in a full system emulator, or in docker (which is at base chroot plus qemu-user).

The HiFive Unmatched they mention from 2021 is expensive, but as soon as the VisionFive 2 was shipped in January 2023 (more than two years ago) for under $100 you've had far better price-performance doing builds on real hardware than in emulation on x86 or Apple Silicon. You just need to either be patient, or else buy more than one of them.

Chinese RISC-V project teases 2025 debut of freely licensed advanced chip design

Re: "hasn’t progressed as quickly as hoped "

China does actually have some high performance chips already, and people who know how to develop and verify and debugs them.

LoongArch, for example. Or Allwinner and Rockchip. The RK3588 is a pretty decent chip.

RISC-V is making moves, but it has work to do if it wants to hit the mainstream

Re: It isn't free

RISC-V isn't about saving a few cents on a chip, it's about 100 companies having freedom to innovate and compete, not just Intel. AMD, Arm, Qualcomm, and Apple.

> If you have some little chip made with older technology that costs only a buck to fabricate saving a dime or two in ARM licensing makes a big difference in your profit margin

There are very popular RISC-V chips that retail for $0.10 in qty 50 (i.e. you have to invest $5 to get that price). Search for CH32V003. There is a retro-PC kitset using that chip -- with more capability than a ZX81, twice the RAM, 100x the speed -- with PS/2 keyboard and VGA connectors that sells for €1 for the whole computer, not just the chip.

https://www.olimex.com/Products/Retro-Computers/RVPC/open-source-hardware

https://www.youtube.com/watch?v=dfXWs4CJuY0

> People need to quit dreaming that RISC-V will come to smartphones (other than maybe the sub $50 market) let alone PCs. It will never happen

Never is a very long time. Both of those are going to happen by 2030.

You can already get multiple laptops using RISC-V processors, including a main board for the high quality Framework Laptop 13. At present they are slow, a similar speed to a late Pentium III or a very early Core 2 (e.g. original MacBook Air). They'll be hitting mid-life Core 2 Quad speeds sometime this year, and early Core i7 (maybe Sandy Bridge-ish) next year, maybe Zen2 / Apple M1 in 2027.

Framework laptops get modular makeover with RISC-V main board

> There's no reason to tape out multi-GHz 32-core RISC-V CPUs. Who would buy them?

The 64 core 2.0 GHz (isn't that "multi"?), 128 GB RAM Milk-V Pioneer started shipping to customers in January 2024. I know a number of people who've bought them. One came up on eBay and I tried to get it myself but there was far too much bidding interest.

If the price/performance/power consumption is right then data centres will snap them up. Arm is making big inroads just five years after the first Graviton machines -- which had the same speed CPUs as that Pioneer, but only 16 cores not 64.

> It'll take years for the adoption to happen.

Adoption will take years after suitable hardware is available, yes. That's why getting fast hardware out is important, and is happening.

> The point is that some company *could* do it if they wanted

Multiple companies *are* doing it, right now. It's just not an instantaneous process.

> ARM isn't somehow inherently faster than RISC-V. That's like claiming one API definition is faster than another. Definitions don't have a speed. Implementations do.

Absolutely correct. Though a bad API / ISA can make it a lot harder. Both Arm (especially 64 bit) and RISC-V are good ISAs. x86 is a rubbish ISA, but sufficient time and money can and has made it fast.

> No, RISC-V is nowhere near as fast as Arm; yes, lots of people regularly claim it is,

No sane person could claim that currently shipping RISC0V is as fast as currently-shipping Arm. It's just not even close.

Take my own primes benchmark [1], for example. The fastest RISC-V right now is the Milk-V Pioneer, at 9.622 seconds (EIC7700 is a couple of seconds slower, btw). AWS Graviton4 c8g does it in 3.075 seconds, over 3x faster.

> or will be within months

Not months, but a couple of years, yes. Announced -- that is design completed and tested in simulation -- RISC-V designs are out comparable to recent Arm designs e.g. SiFIve P870 vs Cortex X.

> or that the differences are trivial.

The ISA differences are trivial, and RISC-V and Arm implementations with similar µarch have comparable speeds e.g. SiFive U74 is very comparable to Arm A55, better than Arm A53 etc.

> Perhaps there is a strict, precise technical definition of this term that I don't know.

Yes. An Instruction Set Architecture is an Instruction Set (that is, literally, a set of instructions that a computer can run, enabling one to write programs using those instructions) that is an Architecture enabling and containing multiple different implementations with different speeds and prices but which run the same programs. The term originated in 1964 when IBM announced on the same day multiple different IBM S/360 machines that all ran the same program binaries, but varied in price and performance by a factor of more than 50x.

x86_64 is an ISA. Ice Lake and Zen 2 are implementations.

Wirth RISC is an ISA, RISC-5 is an implementation -- in fact RISC-4 and RISC-5 are the same CPU implementation as RISC-3 but just with added peripherals: an SPI SD card interface in RISC-4 and PS/2 keyboard and mouse, VGA display, and network (via SPI) in RISC-5.

> For me, that counts as predating RISC-V; YMMV.

You published your article in December 2015, Wirth published his paper in September 2015. I have no idea when Wirth started using the names RISC-0 to RISC-5 himself, but I can't find any earlier publication about it.

The first publication of the name "RISC-V" was possibly “The RISC-V Instruction Set Manual, Volume I: Base User-Level ISA” in May 2011 though the ISA underwent some evolution between then and the compatible with today's chips user-mode spec in May 2014:

https://www2.eecs.berkeley.edu/Pubs/TechRpts/2011/EECS-2011-62.pdf

https://www2.eecs.berkeley.edu/Pubs/TechRpts/2014/EECS-2014-54.pdf

The first commercial RISC-V hardware (a 320 MHz Arduino Uno compatible board) was shipped in December 2016 and I had one in my hands in Moscow the next month. Wirth of course never shipped any real RISC-5 chip, but only an FPGA implementation (in 2015). The RISC-V Rocket core was published and publicly available for anyone to run in FPGA in 2012, and Berkeley of course made a number of test chips for internal use too.

The first public RISC-‐V Workshop was held in Monterey, CA on January 14, 2015 and the second at Berkeley in June 2015. Even before that, the RISC-V team made a splash at the Hot Chips conference in August 2014.

https://riscv.org/announcements/2014/08/risc-v-at-hotchips-26/

So there was a LOT of public RISC-V activity before Wirth published his paper or you wrote your article.

The Oberon language and OS of course dates from the 1980s, and I was using it on a Mac back then. There was hardware at ETH in the early 80s but it was built around the commercial NS32032 CISC microprocessor.

[1] http://hoult.org/primes.txt

> In our opinion, RISC-V is not yet competitive with Arm in performance.

Why opinion? It is simply a fact that currently widely-available RISC-V hardware is around 6 years behind Arm. No one -- least of all RISC-V fans -- would dispute that.

Hardly surprising, since six years ago the RISC-V ISA was still almost a year from ratification / formal publishing. The official initial spec document is riscv-spec-20191213.pdf, the default modern GCC flag is " -misa-spec=20191213" etc. That is still (just) less than five years ago.

The Sifive P550 machines are are starting to trickle out over the next few months are solidly in Pi 4 territory (or even a little better), other than lacking a NEON equivalent.

The SiFive P670 machines based on the SH2380 SoC that will, politics allowing, be out late next year will be fully better than the Arm A76 Pi 5 / Rock 5, which will put them between 2 years (Pi 5) and 3 1/2 years (Rock 5) behind Arm.

> there already was an architecture called RISC-5, which was designed [PDF] by the late great Niklaus Wirth

That is not an ISA. RISC-5 is Wirth's 5th and fastest example implementation of the same ISA, following RISC-0, RISC-1, RISC-2, RISC-3, and RISC-4 all of which implement the same ISA and are presented together in...

https://people.inf.ethz.ch/wirth/FPGA-relatedWork/RISC.pdf

The ISA appears to be called simply "RISC", if in fact it has a name at all.

> There was general surprise and disappointment at the announcement that they'd chosen the StarFive JH7110 SoC

That's silly. The JH7110 is the obvious choice for an initial shake-down board, as the most mature and supported reasonably high performance RISC-V SoC at the moment.

> There's already much more performant RISC-V silicon available, with more coming along soon.

I'm not sure what you mean by "already".

- The TH1520 has been out almost as long as the JH7110, and being higher frequency and OoO does quite a lot better on micro-benchmarks, but in the real world it is often a little slower e.g. building software. It does have the advantage of having a high performance vector implementation, but it's the draft 0.7.1 spec, so needs special handling. (But JH7110 doesn't have vector at all). And the C910 cores have that nasty privilege escalation bug ("Ghostwrite")

- The SpacemiT K1/M1 has real RVV 1.0 vectors, and 8 cores, but they are slow cores. Even using all 8 is only barely faster than the JH7110, and single core is slower. It's also very new, and dedicated boards -- and much cheaper laptops such as the Musebook and DC's own Roma II -- have only been trickling out in the last 4 or 5 months. It doesn't make sense to use it in the initial Framework board, but it makes perfect sense to use it in a follow-up in six months or so.

- the ESWIN EIC7700 is indeed considerably faster (better than Pi 4 in most respects other than NEON) but not really available yet. A few privileged people have early boards, but mass-production shipments of the SiFive HiFive Permier, Milk-V Megrez, Pine64 StarPro64, Sipeed Lichee Pi 5A have not yet started. Again, it's an excellent choice for a follow-up board next year. But sadly no vector unit at all.

- the Sophgo SG2380 will be a fantastic CPU for RISC-V, with the latest ISA spec, OoO, high frequency, high performance RVV 1.0, and leapfrogging the Pi 5 / Rock 5 / Orange Pi 5 generation of Arm boards. Technically, it's a candidate for a follow-up Framework mainboard late next year, but unfortunately it seems to be caught up in a political TSMC/Huawei sanctions mess.

SiFive launches early access for Premier P550 RISC-V developer board

Re: RISC-V everywhere?

> I wonder how it compares to the DC-ROMA Laptop II

Considerably faster, especially per core, but also overall despite the disparity in core counts. But no RVV vector instructions.

You can (or will be able to very soon) buy boards with the same EIC7700 CPU chip much cheaper from Sipeed (LicheePI 5A), Milk-V (Megrez), Pine64 (StarPro64).

Milk-V have also announced the Cluster 08 which can take eight Megrez NX or Jupiter NX (same CPU as DC-ROMA II) compute modules.

https://milkv.io/cluster-08

> Don't want it. RAM not socketed. What's the point of it if you can't add more RAM if/when you need it?

Just like pretty much every other Arm or RISC-V board (at least the ones under $1000), or all Apple PCs for the last four years or Intel's new Lunar Lake both of which have RAM in the PCU package, not even soldered to the board.

It's the future, like it or not.

Faulty instructions in Alibaba's T-Head C910 RISC-V CPUs blow away all security

Re: The instruction they ran is not even a valid RVV 1.0 instruction, let alone RVV 0.7.1

The article is wrong.

The "custom extension" in question is XTHeadVector, which is exactly the 0.7.1 draft version of the official RISC-V Vector extension, and is being called a "custom extension" for political reasons. It was a candidate for being the official version, but we on the working group had some new ideas and changed a few things before calling a slightly later version 1.0.

The so-called instruction the researchers used is not a valid instruction in either THead's documentation or the original RVV 0.7.1 documentation. The field used to specify load & store sizes is simply not large enough to ever have a 128 bit version of that instruction. It isn't even big enough to have a 64 bit version.

The instruction they ran is not even a valid RVV 1.0 instruction, let alone RVV 0.7.1

`vse128.v` is a potential RVV 2.0 instruction. It is not listed in the RVV 1.0 spec, which stops at `vse64.v`.

My GCC 15.0 (WIP) does not allow `vse128.v`.

RVV 0.7.1 has only `vse.v` which stores whatever SEW currently is, and `vsb.v`, `vsh.v`, and `vsw.v` for explicitly sized stores.

There is not even an explicit 64 bit store in RVV 0.7.1, let alone 128 bits.

Why RISC-V must get its messaging right on open standard vs open source

The fastest current RISC-V chips are Chinese anyway

Not noted here is that the fastest RISC-V general purpose machines you can currently buy use the THead C910 core, which is:

1) Chinese

2) actually Open Source (except the vector unit): https://github.com/T-head-Semi/openc910

The fastest off the shelf RISC-V machine currently is the Milk-V Pioneer using the SG2042 SoC which has 64 C910 OoO cores running at 2.0 GHz, with 64 MB L3 cache and up to 128 GB RAM.

Of course this situation changes very fast. There will be several machines using SiFive's P550 cores in several months -- most from Chinese companies, or at least using Chinese SoC (SiFive's own HiFive Premier P550 board). And then at the end of the year the Milk-V "Oasis" (and others from at least Sipeed) using SiFive's P670 cores, but again in the Chinese SG2380 SoC.

There are a several US startups who started work on RISC-V core in 2021-2022 who will have much faster (Apple M1 class or better) cores, but those won't arrive in machines you can buy until 2025 or 2026.

US government reportedly ponders crimping China's use of RISC-V

Re: This is cute

> The first ARM chip powered the first 32 bit desktop computer (Acorn Archimedes)

No. The Archimedes was released in June 1987, by which time the Apple Lisa had been out for 4 1/2 years and the Mac for 3 1/2 years. Both of those are desktop computers with a 32 bit ISA, though implemented with a 16 bit ALU (32 bit instructions took longer) and 16 bit memory bus. But the Mac II was out in March 1987, fully 32 bit in all respects, and three months before the Archimedes.

Even the Compaq Deskpro 386 was out in September 1986, nine months before the Archimedes.

Yes, the Archimedes was fast. At 8 MHz it was a little faster than the 16 MHz 80386 and 68020, due to the better pipelining, allowing 1 instruction per clock cycle on code that worked in registers (no RAM access) and didn't branch, while the 386 and 020 needed on average about 4 clock cycles per instruction. The 68020 also had a small (256 byte) instruction cache, which helped loops. The other two had no caches at all.

Re: This is cute

As you say "Instruction sets are just a compatibility layer, but if you want a high performance system, the compilers, operating systems bus architectures, memory architectures, and the CPU cores have to be designed almost as a single component". I agree.

So, how then is RISC-V shit, given that people capable of building a high performance system, compilers, operating systems, bus architectures, memory architectures, and CPU cores using, say, x86 or Arm ISAs are equally capable of doing the same with the RISC-V ISA.

A concrete example is Qualcomm, who bought Nuvia for their high performance Arm core, then we told (and sued) by Arm saying they're not allowed to use it. Qualcomm have as much as admitted that they are converting that Nuvia core design to run the RISC-V ISA instead.

> what would it take to build an alternative to RISC-V, the answer would be “buy a CPU architecture book, design an instruction set, the build a binutils and gcc (or llvm) for the architecture and port an OS. This is shockingly easy to do.

It's easy to do as a toy. It's not at all easy to design an ISA that doesn't suck, and it costs literally billions to build a production-quality software ecosystem around it.

Re: Switzerland's nice

Uhhh … they did exactly that in March 2020

Loongarch is not RISC-V

Loongarch is not RISC-V. It’s built along similar design principles as MIPS and RISC-V (and the older Longsoon ISA was a direct MIPS copy). Absolutely no one can stop them doing that but it also misses out on the key advantage of RISC-V — the software interoperability.

These US lawmakers don’t know the first thing about computers.

SiFive is back with another 64-bit RISC-V dev board – hopefully

You need to distinguish between an abstract design for a CPU core (which is what BOOM, C910, P550 are) and someone taking that and adding all the other stuff around it to make an SoC, then making an ASIC (chip) from that, and then putting that on a board that anyone can buy and have delivered to their home.

There are a lot of steps between the first part and the final result.

For sure it’s not the first OoO RISC-V. That honor goes to the THead C910 that shipped last year in the quad core TH1520 SoC Sipeed Lichee Pi 4A and other devices) and the 64 core SG2042 (Milk-V Pioneer).

The P550 should be about 50% faster per core than those, and comparable to the Arm A76 SBCs (Pi 5 and the various RK3588). But the Pioneer’s 64 cores should win on anything that can use at least six of them.

Also of course the SG2380 coming at the end of the year with 16 of SiFive’s own higher performance P670 cores is worth waiting for.

Alibaba's research arm promises server-class RISC-V processor due this year

Re: So impressive!

The Sophgo SG2380 chip will be coming out later this year with 16 SiFive (yes, US company) P670 cores, which are in the same class with Arm A78.

That will be the chip to have for a while.

Milk-V say they'll have a board using it starting from $120, but I expect that will be zero (or very little) RAM, no storage etc. Sipeed are talking about $300.

French cloud Scaleway starts renting Alibaba's RISC-V SoC

Other sources -- including photos -- make it clear they are using Sipeed's Lichee Cluster 4A, with each (rather small) box holding seven compute-module style boards. The same daughterboard used in the LicheePi 4A, Lichee Console etc.

The CPUs are slow by x86 standards, about the same as the Arm A72 used in the Raspberry Pi 4 -- or in the first AWS Graviton in late 2018.

Sipeed tweeted that they'll be supplying cloud-suitable boards using SiFive's P550 and P670 CPU cores this year. P670 is around 2x the performance at the same MHz, plus the SG2380 SoC is promised to be actually running at 2.4 GHz (let's see...), so that's another 1.3x.

These are physical, bare metal, servers obviously. You have your choice of three OSes and they are the real OS, no hypervisor.

MIPS snags top SiFive brains to amp up RISC-V business

Re: World’s Most Popular CPU Architectures

Arm and RISC-V have both been very rapidly replacing 8 bit MCUs in new products. They are just SO MUCH more convenient to program than a PIC or 8051, and there is now even no price advantage to 8 bit with both Arm and RISC-V being available in $0.10 MCUs with 2 or 3 KB of RAM and 16 KB flash.

Re: World’s Most Popular CPU Architectures

> And I think RISC-V might be in that league, too.

Maybe not quite, but soon.

In December 2022 at the RISC-V summit we were told more than 10 billion chips with RISC-V in them. I don't know if that was updated this year, but Qualcomm said they shipped a billion chips with RISC-V in them in 2023. Back in 2017 Western Digital announced they would soon be shipping over a billion RISC-V chips a year. I haven't seen updates on that. In December 2019 Samsung said the Galaxy S20 would have RISC-V cores controlling the 5G radio and the camera. Assuming that has continued and spread through the range that's quite a few cores too. Samsung certainly continues to be interested in RISC-V. They are porting DotNET and their Tizen operating system to RISC-V for use (according to job adverts) in future TVs and other products.

Post-IPO, Arm to push purpose-built almost-processors

RISC-V behind but catching up

The initial version of the RISC-V ISA with just basic integer and IEEE floating point instructions was ratified (frozen, formally published) in July 2019, almost eight years after the ARMv8-A spec was published (and which Arm had presumably been working on in secret for some years -- I suspect from around the time amd64 entered the market in 2003).

Ratification was the starting gun for serious RISC-V players.

A handful of chips existed before that -- a few made by students at Berkeley, generally with instruction sets quite different to the final version, the FE310 and FU540 made in quantities of a few hundred ("shuttle run") by some of those Berkeley students at their SiFive startup, and one commercial microcontroller, the Kendryte K210 made by Chinese company Canaan which specialises in BItcoin mining ASICs. Canaan checked out the then current snapshot of Berkeley's "Rocket" RISC-V core and built an SoC around it.

A couple of reasonably high performance RISC-V cores, the SiFive U74 and the THead C910 were announced right around RISC-V ratification in 2019. The C910 is similar to Arm's A72, as found in e.g. the Raspberry Pi 4. The U74 is similar to ARM's A55, simpler cores that can approach A72/C910 performance (and significantly better than A53) but with much lower silicon area and energy usage.

Multiple low cost RISC-V SBCs have come out this year using the U74 (JH7110 SoC) and C910 (TH1520), plus there is a 64 core C910 SoC (SG2042) that will be on boards shipping to retail customers before the end of the year (vendors have had EVBs since March).

So that's basically four years behind the Raspberry Pi 4, both for announcement of the cores (2015 vs 2019) and SBCs shipping (2019 vs 2023).

The Milk-V Mars (JH7110) is available starting from $39, with a Pi CM4-compatible board starting from $34. The Milk-V Meles (TH1520) is faster and starts from $99. Other companies including Sipeed, Pine64, and BeagleBoard are also shipping SBCs (and a tablet from Pine64) using one or the other of these chips, but so far Milk-V have the keenest pricing.

2024 is going to see RISC-V boards competitive with the RK3588 Arm A76 boards such as Radxa Rock 5 and Orange Pi 5 [Plus]. Those will be about two years behind the similar Arm boards.

Multiple companies ranging from SiFive to MIPS to Jim Keller's Tenstorrent to Ventana have RISC-V cores formally announced (or very close to it) that are in the Neoverse to Apple M1 range.

Enter Tinker: Asus pulls out RISC-V board it hopes trumps Raspberry PI

Re: where some high speed SRAM is located

> Err, is it the same memory that shows up in every virtual address space? wouldn't that be a huge security/stability risk?

Exactly! If this is actually correct (and it's being discussed on the Linux mailing list) then it's just an awful blunder on the part of Andes.

https://lore.kernel.org/all/[e-mail]/

They want to change the address for statically-linked binaries, to start above this address hole.

OK, sure, that will work with things they compile themselves, or on their board, but not for any binary copied from another RISC-V system WHICH SHOULD WORK.

To solve this you'd need to have the OS copy that 128 KB of RAM in and out on every process switch (or address space switch), at least if either the from or the to process has that memory range in their page table. Slow, slow, slow.

Just an awful bug in that Andes CPU core, if this is all true and not some misunderstanding.

Re: where some high speed SRAM is located

It is completely normal to have a few KB of ITIM and/or DTIM on both ARM and RISC-V chips. Often (e.g. on all current SiFive cores) you can programatically decrease the size of the L1 cache and use the rest of it as scratchpad.

That's in physical address space.

What is wrong here on this Andes core is that this shows up in EVERY virtual address space too. That just completely breaks what a virtual address space is supposed to be. You're supposed to be able to map any virtual address to whatever physical address the OS wants. Not to have part of it (128K) mapped directly to physical.

On a normal ARM or RISC-V or x86 chip (or any other), you can always choose to map a certain part of multiple (or all) virtual address spaces to the same physical addresses. It's normal for this to be done for the OS kernel's RAM, for example. It is mapped the same in every process, but protected so only OS code can read/write it.

But that's a CHOICE.

This Andes core doesn't give you a choice, and furthermore, puts that area in a commonly-used address range.

Re: Look up StarFive 2

> Someone dug deep into the source code commits for the JH7110 and found that they could possibly do 1.75GHz, but you would probably need proper cooling.

As it does 1.5 GHz without a heatsink of any kind, and a lot cooler than a Pi 4 -- I haven't been able to get mine over 68 C with a heavy make -j4 build taking over two hours -- it can probably do a good bit more than 1.75 GHz with "proper cooling".

Re: Look up StarFive 2

> I don't see how a single core 1 GHz CPU can get close to 80% of the 4 core 1.5 GHz Raspberry Pi 4 CPU. Can you expand on how this is done?

It doesn't, obviously. That post is very badly phrased.

The Asus Tinker V has a 1 GHz single-issue core.

The StarFive VisionFive 2 has a 1.5 GHz quad core dual-issue in-order CPU, similar to an ARM A55 at 1.5 GHz, and about 80% of an A72 at 1.5 GHz -- except for lacking the NEON SIMD found in the ARM chips.

Re: Look up StarFive 2

> Said to have the performance of a top flight 2016 smartphone - sufficient processing power to do lightweight computing.

The better comparison would be an SBC with RK3566 with quad A55.

Re: Yikes.

> The closest board on there is the BeagleV StarLight JH7100

300 of those were made and distributed for free to developers in April 2021. I was lucky enough to get one. No more have ever been made.

They were supposed to go into mass-production with a different SoC, the JH7110, in September 2021, but that didn't happen. Instead, a very very similar board, still with the JH7100, has been sold as the VisionFive v1 since December 2021, and the VisionFive 2 with JH7110 started to be delivered to people in January and February 2023.

Re: Wrong

>Starfive are upstreaming all their work for the VisionFive 2 to the 6.3 kernel. Looks to me like they planning future support.

Indeed so, but StarFive with their SiFive core based SoC are completely different to Asus with their Andes CPU core.

Also, I just yesterday learned that this Andes core has a major major flaw in not correctly implementing the RISC-V spec. It appears that virtual addresses between 0x30000 and 0x4FFFF do not (unlike all others) get mapped to physical addresses via the page table and TLB etc, but directly access the same PHYSICAL addresses, where some high speed SRAM is located.

This completely screws any OS which puts anything in those virtual addresses. Such as ... oh I don't know ... statically linked Linux binaries. I just checked a HelloWorld kind of program on my VisionFive 2 and the code starts at 0x103e0 and ends at 0x49bab ... so smack through that unmapped region.

Could RISC-V become a force in high performance computing?

Re: RISC-V is inherently high performance

The problem is that branch delay slots and load delay slots only made sense for a single micro-architecture -- the first single-dispatch in-order one, generally with 5 pipeline stages.

As soon as you did anything else ... dual or triple issue in-order, or OoO, the delay slots not only didn't help any more but also actively made implementations harder because of the screwed-up semantics.

Re: A mixed blessing?

RISC-V SBCs with draft 0.7.1 of the Vector ISA are currently available starting from $17 (Lichee RV 1 GHz 512 MB RAM https://www.aliexpress.us/item/3256803408560538.html)

That's the in-development spec as at the middle of 2019.

The final 1.0 Vector spec is incompatible in detail but about 90% or 95% the same binary opcodes and the same semantics. Close enough that 0.7.1 hardware gives a good head start. Many useful algorithms such as memcpy(), memcmp(), strlen(), strcpy(), strcmp() and so forth are binary compatible between 0.7.1 and 1.0.

There is no reason that in time RVV 1.0 implementations won't be available at similar price-points. It's not any harder to implement, just a few minor details were changed sue to feedback, experience using 0.7 and 0.8 and 0.9 and 0.10. (NO one has commercially produced anything except 0.7.1, but intermediate versions were implemented in the Spike emulator and in GNU binutils etc and programming experience gained with them.

If RVV eventually makes its way into supercomputers (and it seems that it will), then you're going to be able to test your supercomputer code on a $10 or $100 SBC or $1000 laptop.

Re: Only if China pushes hard

“That said, RISC-V CPU performance is still far behind x64 and arm64.”

Obviously, because RISC-V started much later.

Currently off-the-shelf RISC-V SBCs are 3-4 years behind ARM. When the Intel/SiFive Horse Creek product ships in around six months, it will be a little over 1 year behind the RK3588 ARM boards. Ventana and MIPS have announced chips near current x86 and Apple chips, so I guess they’ll be shipping in around 2 years.

RISC-V is several years (not decades) behind, but catching quickly.

Re: RISC-V is inherently high performance

“AAarch64 is probably the best ISA going since it was conceived so recently - more recently than RISC-V.”

The ARMv8.0-A ISA was published in finished form in October 2012. The RISC-V ISA was ratified and published in frozen form in July 2019, with important additions to bring it to parity with ARMv8 in November 2021.

People usually give RISC-V’s newness as a disadvantage, so this is a weird argument from you, especially given the facts are the opposite.

Design of RISC-V started in 2010, a couple of years before ARMv8 was published. The *design* of ARMv8 clearly started much earlier. I don’t think anyone has really said how much earlier, but I suspect around 2003-2004 when amd64 made it clear it wasn’t going to be an Itanic-only future.

Twitter tweaks third-party app rules to ban third-party apps

Is Twitter's own app still crap? The web site is for suer utterly unusable for me. I've been using Tweetbot forever -- I don't even know how long. Ten, twelve years? For me, Tweetbot IS Twitter.

My needs are very simple. I want to read every tweet made by anyone I follow (or at least original tweets and replies to people I also follow), in chronological order. I want the app to remember what I have read and what I haven't read. I don't want to see tweets by people I don't follow, or tweets "I might be interested in", or sorted in some way other than chronological.

I don't need something to "manage" my experience on the assumption I can't read all the tweets from people I follow. I can. I trim my following list as needed to ensure I can.

Biden wants SpaceX to beam internet to Iran amid uprising

Are the companies supplying rifles and HIMARS and HARM and Hummers to Ukraine expected to simply donate them? I don’t think so. So why is Musk expected to?

An individual or private company shouldn’t get directly involved in wars. That’s very dangerous to them. If the US or EU governments buy stuff from SpaceX then donate it, that’s very different from SpaceX doing it themselves.

The terminals and service sent to Ukraine cost twice as much as regular home terminals because they are the equivalent of business accounts, which provide a higher level of service.

SpaceX is at very real risk of going broke at the moment. They need to expand Starlink hugely to get cash coming in, but they can’t do that until they get the Starship/Superheavy rocket flying. They have literally warehouses full of satellites that have been built but can’t be launched because they don’t fit inside Falcon 9.

Also, as noted, Starlink can now operate in Ukraine because the Ukrainian government gave (begged) them a license to. That’s not the situation in Iran.

China has recently been demanding assurances from SpaceX that they will NOT enable Starlink in China. I’ll bet Russia doesn’t want it either.

If Musk goes against those kinds of people then he’s going to need Putin-level personal security.

China may prove Arm wrong about RISC-V's role in the datacenter

Re: Poor article

>The article then goes on to say that both CPUs are possible but there's currently no indication that there's anything remotely as powerful as ARM or x86 out there or on the horizon.

That's just not correct.

It is well known in the industry that RISC-V startup Rivos, for example, has been founded by some of the same people who founded PA Semi, which as bought by Apple in 2008, and created Apple's A-series chips and the M1/M2. A number of other engineers who worked on the M1 have also gone to Rivos. Apple is suing them for taking "too much" information with them.

Interestingly, Apple is not asking for an injunction to stop Rivos from working, or even fixed damages, but for a ROYALTY on sales. That means Apple expects them to be successful. They have the people, they have the funding.

The way these things go with Rivos being founded in May 2021, an M1-class (maybe better) RISC-V will emerge from them probably around 2024-2025.

There are others too, but that's the slam-dunk example.

Arm execs: We respect RISC-V but it's not a rival in the datacenter

Re: Toast

ARM's "every instruction is predicated"?

Looked great in a couple of hand-picked examples in 1985: GCD, software emulation of missing multiply and divide hardware instructions. But not so much in general code.

They didn't include predication at all in Thumb, just traditional conditional branches.

Thumb2 (ARMv7) added back a limited form -- maximum 4 instructions in a row predicated by the same condition or its inverse, controlled by an extra instruction preceding them.

Predication is entirely absent from 64 bit ARM.

Re: More bad news for Intel

Every simple foundry customer project isn't going to be given an Intel platform name like "Horse Creek". This is something more.

Intel bags deal to make chips for MediaTek, that other Android processor designer

When a company such as MediaTek does a "tape-out" and sends the resulting physical design files to the chip maker, there is absolutely no easy way to tell what the data on the "tape" represents, whether it has x86 cores, ARM cores, RISC-V cores, or just a lot of random logic.

Airbus flies new passenger airplane aimed at 'long, thin' routes

Re: Long and thin eh?

Yes, A380 is the best, but you can't always get one.

I would much rather travel in an A320 for 11 hours than in a B777 with 3-4-3 seating. I absolutely hate those things.

I love the 16 hour Dubai-Auckland A380 flights (17 the other way). Far far better than having a stopover and getting back on the same plane.

Sadly it seems this stretched A320 won't even make Perth from Dubai, let alone Melbourne or Sydney. But either Singapore or Bali would serve as a reasonable halfway point to NZ.

It also isn't going to manage Auckland to LAX or SFO. Other than the 747-400 (which have long gone from the route) the best time I've had between NZ and the US was with Air Fiji with their A330s (with a stop in Fiji of course).

I haven't yet had a chance to fly in a 787 so I'll reserve judgement on those.

Just someone kill the 777, please. Or at least make the airlines use 3-3-3 seating as they were designed for.

Will this be one of the world's first RISC-V laptops?

Re: Some serious questions.

Just about everything in your post is wrong.

RISC-V was not introduced 12 years ago, some students and their professor had a crazy idea in a pub to START it 12 years ago. It was essentially introduced to the world a little under 7 years ago.

Dave Patterson invented the term "RISC" and the first RISC I CPU around 1980-1981, not 1990. I can only assume you weren't born at those times and consider them prehistoric.

ARM does NOT allow you to add or remove things from their CPU core or the instruction set. Of course you can add whatever you like else in the SoC, as you don't license that from ARM and ARM doesn't make such IP.

The Raspberry Pi is very far from standard. There are simply a lot of them. (Compared to other SBCs, not compared to phones or tablets)

Re: Cool...

Look up "binfmt_misc". I've been using it for many years to run x86, ARM, RISC-V (and others) binaries transparently on whatever board I'm currently using.

Slower than native, of course, but much faster than Python.

Re: Some serious questions.

I don't know why you think it appropriate to look at what is clearly a personal project of a handful of people and extrapolate that to OoO RISC-V cores from companies such as SiFive, Alibaba, Andes employing experienced CPU designers who have previously worked at ARM, Intel, AMD, Apple ...

It's been known for quite a few years now how to avoid Spectre/Meltdown and that it's pretty easy if you incorporate that into your design from the outset.

Here's something from four years ago: https://www.youtube.com/watch?v=yvaFpNNLkzw

The presenter designed OoO BOOM as a student, later ET-Maxion at Esperanto, and now works as a core designer at Intel.