Catching up to the mainframe
Sounds like intel (and presumably its competitors) are finally catching up to IBM's 360+ architecture mainframe systems with respect to offloaded I/O function. In the 1960s IBM designed the 360 to use Channels (I/O subsystems) to perform I/O independently of the CPU. When soon after they introduced the first PC they tried to improve their I/O performance with their MicroChannel adapter, but it required high-precision clocking and was expensive to produce, so never got into competition.
Channel architecture allows the mainframe CPU to pass just device information and main memory buffer address to the channel, then continue running other tasks until the channel interrupts when its I/O operation is completed. I presume that these smartNICs/IPUs/DPUs will provide something similar to IBM's Channel subsystem?