Reply to post: still not getting it

RISC-V needs more than an open architecture to compete

Anonymous Coward
Anonymous Coward

still not getting it

The commentards that is.

Rupert is 100% on the mark in this article.

It doesn't matter how much pro-RISC-V propaganda various outlets - including the RISC-V Foundation - spit out to the public. They're playing to the gallery that can't tell the difference between an ISA Spec PDF and a chip.

Extolling the virtues of RISC (as in Reduced Instruction Set) ISA's is nice, and might make one feel good, but it's not a chip that can be seated on a board and make a decent performance server.

For RISC-V to provide a viable and competitive alternative to x86_64, it needs to prove itself as realized silicon, not just PDF specs on GitHub, or atta boy enthusiastic statements.

To date, no-one has produced a viable RISC-V alternative to Xeon. Play-toy SiFive development boards don't count.

I have nothing against RISC-V. It's an updated version of MIPS, or SPARC without register windows or delay slots. Yay!

RISC-V's problem is that it's playing second fiddle to ARM, and ARM has been playing second fiddle to x86_64 since ... 1999?

ARM has already sold their ARM64 licenses to just about everyone interested in buying one. And? Where are they today, and where are they going? Nowhere, that's where.

If this RISC-V alternative to x86_64 ever materializes, it will be in the US, and maybe the EU. Not in China, not in Russia and not in India. The only thing these three countries have proven so far, in terms of silicon engineering, is that they massively suck at it, sanctions or no sanctions.

The fundamental problem being: no-one - not even ARM themselves - has managed to make a compelling case why ARM64 is worth tossing out hundreds of millions in x86_64 infrastructure investments, and replacing them with ARM64. So, where's the corresponding case for RISC-V?

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