original author
Author of the paper is here vvv:
Thanks a lot for your inputs guys, they are appreciated. May be few things I want to clarify here:
- we didn't claim it a vulnerability, but a hardware flaw which leads to a certain predictable change in the uarch state;
- according to spectre/meltdown taxonomy (https://pure.tugraz.at/ws/portalfiles/portal/28987078/transient_attacks.pdf) this behavior falls under meltdown type; We also say that classical meltdown doesnt work bc the certain design in AMD cpus. At current point, ofc classifying it under the meltdown class is very academical, and doesnt lead (and never supposed to be) to a new "AMD MELTDOWN" boom. I admit, that classifying it under meltdown class brought too much attention, and might feel overhyped, so all your concerns are well understood.
- Same address space: We provide only synthetic scenario, where such a flaw in hardware may lead to unnecessary side effects and can be exploited for sandboxes only ( no cross address space).
- cynical reasons: We tried to push the paper to EuroSec 2021 Workshop, but got a weak reject due to lack of full exploit, so I tried to write a paper in a way it will be sold there, thats the only driver for writing this paper. No vendors or any other parties were behind funding or whatever. I did this research in my "free time" as a research assistant in uni. I spend some time on it and I also believe that these are interesting results for sure. Moreover, AMD admitted the presence of the problem and agreed that it MIGHT have effect in real systems.
Actually I personally think that it is a laudatory paper for AMD, bc we show that meltdown (at least how we understand meltdown today) does not and will not work on AMD cpus.
Biting the hand that feeds IT
