Re: VHDL's still a verbose horror, then.
VHDL and Verilog are NOT programming languages. They are Hardware Description Languages. It's unfortunate that Verilog looks like C.
There is no "run time". The text describes the parts (components) and how they connected. It's a textual exact alternate to a circuit diagram. It's the easiest way to do FPGAs. If you are doing a logic ASIC, it makes sense to do it as an FPGA first. The FPGA tools can later produce the files for a custom chip rather than the FPGA configuration, usually loaded at power on from Flash (not executed).
Even with a free chip, I'd want to use an FPGA on a ready made evaluation board first. Then it might actually work when I've debugged the FPGA. The actual ASIC (custom chip) will not usually need as many pins and will usually use a tiny fraction of the power.
Analogue is harder. RF Analogue is much harder. Unsurprisingly while you can get an FPGA with an actual CPU (rather than defining one) as well as the usual multipliers, PLL, RAM Blocks (to implement gates) and RAM to define the interconnections, there is little in the way of analogue and less RF.
A Math AI seems a waste. One, AI is mostly marketing hype and two, better to develop such a thing as an FPGA.
The interesting application of this is designs that can't be done purely as an FPGA. You'd still make a prototype using suitable ICs, transistors and maybe a CPU and FPGA on a PCB first to debug and test.
Biting the hand that feeds IT
