Reply to post: Re: "transistor layouts for FPGAs"

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Re: "transistor layouts for FPGAs"

The current high level synthesis tools supported by XIlinx are Vivado and Vitis which do indeed have support for C, C++ and System C.

The problem I have with trying to introduce this into C is that it encumbers the language with something that outside of hardware optimisation for FPGAs (and ASICs) is not going to be useful and simply muddies the waters.

When writing Verilog or VHDL we state the size of the fields required explicitly anyway; the problem arises when using high level syntax (in whatever language) in a HDL environment (with the inherent specifics of what data types are available) for something that was never originally intended by the language.

There could be an extension for the FPGA tools where the necessary size could be stated; there is nothing stopping the FPGA tool vendors from adding such an extension (they would need to advertise it as C / C++ / SystemC / <insert your favourite language here> with hardware extensions).

I understand why we use high level synthesis (take a look at the OpenSparc verilog source if you want to see how complex, and therefore bug prone, a large project can be) and on today's monsters such an approach is necessary.

This does not, however, justify adding this formally to C (my view, obviously).

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