Re: Been here before
"I well remember the RISC anxiety at Intel when I worked there 35 years ago."
And when Intel moved from pure x86 CISC to x86 CISC instructions decoded to µops to run on a RISC like architecture with the P6, what happened to that anxiety? Sure, Intel hedged it's bets with Itanium/VLIW but reality wasn't kind to that...
Biting the hand that feeds IT
