Re: Oh dear.
"One of the problems is the nm nomenclature - 7nm isn't really 7nm. My understading is 28nm was the last 'true' size."
It's worse than that...
The process node used to reflect the minimum gate length, but this stopped at 45nm. As everyone's processes below this node size have been heavily customised for their own workflows/design guides, the nodes are now driven by Moores law - a 50% increase per mm2 is a half node and a 100% increase per mm2 is a full step.
But realistically, Moores law died around the time frequency scaling stopped being the predominant factor in CPU upgrades.
Ref:
Overview
https://en.wikichip.org/wiki/technology_node
Divergence at 14nm (where known) and 16nm for TSMC:
https://en.wikichip.org/wiki/14_nm_lithography_process
https://en.wikichip.org/wiki/16_nm_lithography_process
Biting the hand that feeds IT
