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And here's Intel's Epyc response: Up-to 56-core, 4GHz 14nm second-gen Xeon SP chips, Agilex FPGAs, persistent mem

cb7

"They can’t patch all of it, because the only way to completely get rid of it is to completely get rid of speculative execution in caching, and if you do that, your shiny modern Core i7 performs as well as a ‘286"

A slight exaggeration, but I'll say it again. There's merit in developing cheaper memory that doesn't need 16 clock cycles to get dressed everytime it's asked to go fetch some data.

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