Re: 30-40% gain from HT.
As always, "it depends." I worked on the STI consortium's Cell microprocessor, which had a 2-threaded PPC core. I can easily see 30-40% gains in workloads, which is different from system level improvements. The wait time for an L1 cache hit is typically 3-4 cycles. L2 will likely run you near 20. That, by itself, is a lot of time try to fill in with computations for a single thread.
Then there is the matter of floating point instructions. They ran the numbers, and the SPUs were designed with enough registers (128, AIR) to keep six threads of computations running on a single thread of execution. So a floating-point intensive workload will quite easily see even speed improvements >50% for two threads.
General system speed improvements will drop substantially (I very much believe the 10-15% there) because of cache contention, and a lot of l2 fetches will just drain your execution units regardless.
Biting the hand that feeds IT
