Reply to post: Re: Gosh, CISC processors too slow for low level HW access so design RISC processor in FPGA

Cloud-stitching startup pitches NVMe FPGAs for SSDs

phuzz Silver badge
Trollface

Re: Gosh, CISC processors too slow for low level HW access so design RISC processor in FPGA

But if it's not Turing complete then how will the developers use {insert flavour of month language here}?

Plus the sort of people who can program a finite state machine probably don't use agile or devops or whatever buzzword is getting VC funding this week.

Basically they're just not cool.

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