Reply to post: Gosh, CISC processors too slow for low level HW access so design RISC processor in FPGA

Cloud-stitching startup pitches NVMe FPGAs for SSDs

John Smith 19 Gold badge
Unhappy

Gosh, CISC processors too slow for low level HW access so design RISC processor in FPGA

What is it about modern HW designers?

"I can't do it without a fully Turing complete processor in the chip. I might get into problems I can't solve."

Handy hint. Most low level protocols can be handled through Finite State Machines. The issues are error handling (which should be infrequent enough you can escalate to a higher level of processing) and the number of states, but state compression tools and design approaches have existed for decades.

Not really seeing the benefits here that scream "I need this in my life, NOW."

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