"I could see using a smaller amount of DRAM and paging from a phase change backing store, thereby saving power. "
That missed the point that DRAM is a bigger bottleneck to performance than anything further down the chain.
CPUs spend most of their time waiting for ram to catch up. The fact that storage past that point is a few hundred/thousand times slower only matters when loading in data or apps.
PCM and friends are good as a rival to keep spurring flash along (even if they never are commercially viable, they keep development of existing tech going), but what's sorely needed _right now_ is affordable off-cpu memory with random access latency of less than 10ns, preferably under 5ns