Reply to post: Re: I'd have assumed that their test code suite would catch something like that...

AMD to fix slippery hypervisor-busting bug in its CPU microcode

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Re: I'd have assumed that their test code suite would catch something like that...

I think it's obviously a fairly trivial and straightforward exercise for the Test Dept boffins at AMD to semi-automatically create

This isn't a bug that's caused by "Execute instruction X followed by instruction Y and get the wrong results".

It's a very precise timing bug between an NMI and the processor being in a certain state. These corner cases are *very* hard to find and reproduce.

As several other commentards have noted, CPUs nowadays are *very* complex and testing every state is almost impossible.

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