Genuine question!
Back in the dim and distant, when I was messing with Z80 CPU dev kits with PIO's for my HNC, the PIO control registers (to generate NMI's on particular input combinations etc.), were at fixed addresses and not mapped (or remappable) to memory locations. I realise I'm comparing a dingy to a supertanker, but why on a Pentium class CPU is the APIC control register mapped to memory and not at some hard coded address which is off limits to anything other than the SMM?
Biting the hand that feeds IT
