Re: Quite a challenge
The 6502 does everything in 8-bits width, except addresses. An opcode byte is optionally followed by an 1 byte immediate value, or a 1 or 2 byte address. I'm guessing that it has 2-bit field in the instruction byte that causes it to load 0, 1 or 2 following bytes to a register determined by rest of the opcode (and increment the PC). If performance is no big concern, shouldn't this operand loading sequence be implementable with a simple state machine? Though I must admit my knowledge about CPU design comes from one mostly-forgotten university course a quarter-century ago... (the final exercise was creating a paper design, which was not even simulated, never mind built.)
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