Re: Stanford MIPS ???
"This design eliminated a number of useful instructions such as multiply and divide ... the chips could run at much higher clock rates."
Is Wikipedia the best you can quote? Especially when it is wrong? For reference I cite this instruction set summary, specifically page 59 (page 5 of the PDF). Do you notice how multiply instructions are included?
In practice, the advanced compiler design, much higher clock rates and cheaper silicon didn't translate into a fundamental advantage in end-user speed.
Err.. no. You have also bypassed the greatest single argument of the RISC/CISC debate: the argument for RISC isn't that compilers are smart, but that they are dumb, and indeed still are as the Niagara example demonstrated. Give me a single example of a C language statement that will be compiled down to an XLAT instruction. If you can't what is is still doing there except for backwards compatibility?
And yes it was that much faster in real world conditions. MIPS wasn't appreciably faster than 386 in terms of clock speed, the difference was a simple 1 clock/1 instruction rule as opposed to an average of 7 or 8 clocks per instruction on 386. The Programmer's Reference Manual is still out there if you want to look that up.
It turned out, firstly, that you could get the same clock speed on silicon that did include "multiply and divide"
Which MIPS did.
that you could implement in silicon the compiler techniques that Stanford MIPS pionered to work around the limitiations of their simplified-instruction, deeply-pipelined design.
Do you actually have any clue about what you are talking about here? MIPS was a five stage pipeline. How is that deeper than 20+ stages? You've used a clearly incorrect reference to "debunk" one example and in the process shown yourself to be pig-ignorant of the entire discipline.
Once again: reality does not change according to what you want to be true. Next time try coming up with some valid arguments.
Biting the hand that feeds IT
