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Next years CPU faster than last years. Makes a fine space heater too.
Intel's latest plan to ward off rivals from high-performance computing workloads involves a CPU with large stacks of high-bandwidth memory and new kinds of accelerators, plus its long-awaited datacenter GPU that will go head-to-head against Nvidia's most powerful chips. After multiple delays, the x86 giant on Wednesday …
The data is not entirely unique every cycle so 1GB is fine. In truth I feel we're at a point where the CPU is the limiting factor. 20 years ago, in 2002, it was the RAM that was the limiter. I know nothing of the technicals but it's clear that the latest RAM specs are beyond what CPUs are utilizing. Well, a single CPU at least, as I guess RAM like HBMe2 is designed to handle the max bandwidth of multiple CPUs simultaneously (well, at least 2).
Each HBM2e stack (in this case a stack of 8 DRAM dies) has 16 pseudo-channels each of which is an independent chunk of 1GB address space (kind of like a DDR4 DIMM, or half a DDR5 DIMM). So these Xeons must have 4x HBM2e stacks integrated in-package.
In an ideal world then, the data would be laid out in 56 pseudo-channel sized chunks (since 56 cores are present) so that each core has its own working storage.
Compared to DDRx channels, that also means that the access pattern on any one pseudo-channel should be more efficient as long as the application code for each core is optimized to generate predominantly sequential memory accesses.
Although it's a while since I've worked on HPC code, that figure of 1GB/core is probably reasonable because modern HPC is designed to scale out over huge numbers of cores. So the HBM advantage is either (a) HPC runs finish faster or (b) since today's performance increases come mainly from increased core count, use more cores to solve bigger problems in the same time.
That's apparently how it is with this "Max", at least do you see proof otherwise? Apple's is gddr4/gddr5 I believe... or am I wrong about that too? I thought Apple's M2 was a SoC that has pretty much hit a wall for future performance uplifts, just like most ARM based SoCs (and x86 for that matter).
Apple's description of M1/M2 as having "high-bandwidth memory" confused me too - I thought they meant HBM the technology rather than generic memory that has improved bandwidth. HBM the technology (JESD235A/B/C) has been around for a while - most notable use up til now has been in Nvidia's data centre GPGPUs like A100.
Dead tech since on Jan 10, intel is switching to pay-as-you-go processors.
Any datacenter fancy paying $50/month PER CPU just to use the processor they purchased for $1000+ ?
Imagine a supercomputer, with 100,000 CPUs. having to BUY the processors..so there's your first $100,000,000
Then a "subscription" fee of $5,000,000 a month JUST to keep the CPU's features active.