Intel’s smartNICs probably aren’t for you (yet) says Intel Unless you happen to be running a cloud or hyperscale datacenter, Intel’s infrastructure processing units (IPU) probably aren’t for you, at least not yet. Accelerators, like Intel’s Mount Evans chips, represent an extreme point on a spectrum. The IPU was built in collaboration with Google for their datacenters, Nick McKeown, …
“I think what is perhaps even more important, dare I say, than the device itself, is the software ecosystem that grows up in support of it”
No, really ? Ya think ?
Gosh. Somebody call Monkey Boy. The 80s has finally found someone who listened.
For servers with high network traffic smartNICs may be useful.
At work we have perhaps 40-50 VM's per server, and all are microsegmented into their own virtual LANs, with only the minimum ports opened between them as needed. Many servers talk to each other via network and all network traffic is routed through external firewalls.
If you had a firewall inside the virtualisation server, you could cut all that extra north-south traffic, and thus save money in the network gear. Network wouldn't be as congested and latencies could be lowered.
You can already install software routers/firewalls and run them as VM's, and route all VM traffic through them. Depending on your requirements, something simple such as pfSense could work. If you needed content scanning/packet inspection (L7), a virtual firewall could really eat into the processing capacity of the VM host itself, which would be bad. In VMware load balancing scenarion where DRS could move any VM to any host in a cluster, you would need the software firewall in every host, and the configuration would need to be kept in sync as well. If it is a commercial solution - expect to pay for each host and then some.
If these SmartNICs can do this without any meaningful performance penalties, and their management isn't a total PITA, they could be quite useful. They will likely cost a lot of money, but so do other solutions as well.
I can imagine a situation in which processing devices become rather simpler and, for example, OS code (or its equivalent) runs on a different device to user-mode code - who wants all that mode switching and cache contention - merely orchestrating the operation of the user-mode devices via some sort of control plane. In this model, all processing units would essentially be of the same class, simply fulfilling different roles and potentially having different processing power, or that power being divided up in different ways. The challenge in all of these scenarios, though, is memory access.
Sounds like intel (and presumably its competitors) are finally catching up to IBM's 360+ architecture mainframe systems with respect to offloaded I/O function. In the 1960s IBM designed the 360 to use Channels (I/O subsystems) to perform I/O independently of the CPU. When soon after they introduced the first PC they tried to improve their I/O performance with their MicroChannel adapter, but it required high-precision clocking and was expensive to produce, so never got into competition.
Channel architecture allows the mainframe CPU to pass just device information and main memory buffer address to the channel, then continue running other tasks until the channel interrupts when its I/O operation is completed. I presume that these smartNICs/IPUs/DPUs will provide something similar to IBM's Channel subsystem?
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