Samsung beats TSMC to be first to produce 3nm chips

Samsung has started production of chips using its 3nm fabrication process, beating rival TSMC, which expects to begin making chips with its N3 node generation later this year. The resultant chips are claimed to reduce power consumption by up to 45 percent and improve performance by up to 23 percent, with further gains promised …

[Andy The Hat]

Surreal ...

When I started "they" were raving on about the potential of ramping production of incredible, "sub micron" chips ... Hell I feel old.

[Yet Another Anonymous coward]

Re: Surreal ...

I was impressed looking at 2um gates on an etched chip under a microscope

[Roj Blake]

Re: Surreal ...

For the purposes of comparison, the diameter of a hydrogen atom is around 0.11nm

[Snake]

Intel

must be feeling rather humiliated right now (even more so than their 10mn failures).

[Anonymous Coward]

Bragging rights

These quoted feature sizes are pretty misleading though, it's no like that is the feature size for full logic gates. Being first to shrink one aspect of positioning or trace width isn't nothing, but as Sammy's announcement concedes, the initial draft of it's new process is going to have significant current bleed issues.

Doesn't by any means make it useless, just that their more mature process will be the one that starts pulling market share. TSMC and Samsung are both on track there.

[Pascal Monett]

3nm, 2nm, 1nm

When are we going to start counting atoms ?

And hey, promising better performance in the next revision when you're not done building the first one ?

I think the industry needs to stop behaving like there hasn't been 50 years of progress. We're practically at atomic scale. I've always read that, at that scale, having a functional gate is much more difficult because electrons have a tendancy to not understand barriers.

Now, I'm not saying this is a problem that cannot be solved. I'm sure there are many people much more intelligent than me who are looking at ways to solve that, but we're getting real, real close to the physical limits of the Universe here, so you might want to dial down the hyperbole a bit.

[Greg 38]

Eye protection

Always amazes me that Samsung does not require the use of safety glasses in their fabs. I've worked in several fabs including Intel and eye protection is absolutely required even in engineering and FA labs.

[IJD]

Unfortunately for Samsung their 3nm GAA/nanosheet process had worse PPA (power performance and area) than TSMCs 3nm FinFET process, as well as having lower yield.

So good for bragging rights, but not customers or business...

[QLord]

TSMC 3nm Has ALL Top 20 Foundry Customers

What are the odds that after years of embarrassingly low yields from Samsung's 5nm and 4nm chips, which are using DECADES OLD FinFET technology, that suddenly their BRAND-NEW Gate-All-Around (GAA) technology will have yields greater than 25%?

Especially since eight (8) weeks ago, it was reported that Samsung's BRAND NEW 3nm GAA yields were around 15%.

Ask Nvidia or Qualcomm if they are taping-out any Samsung 3nm chips, after getting burned by Samsung claiming that their 5nm and 4nm yields where 70%, when they were actually closer to 25%.

I’ll bet they have ZERO 3nm foundry customers, for the foreseeable future.

It’s extremely unlikely that Samsung’s 3nm yields have improved much from eight weeks ago when it was reported to be 15%, considering the additional complexity of their NEW GAA construction.