Proposed RISC-V vector instructions crank up computing power on small devices

RISC-V looks set to be extended to bring more computing power to applications on smaller devices. The Zve collection of software instructions, right now under public review, provide vector math processing for embedded devices and microcontrollers. RISC-V is an open-source, royalty-free instruction set architecture for CPU …

[Tom 7]

Nice

I was somewhat impressed by the SIMD instruction speedups on the RaspberryPi ARM machines though the compiler/coding infrastructure was a bit tricky to work through - this was a while back I need to revisit!

If the RISC-V stuff is as good then NVIdia will not be happy, which is a good thing!

[nautica]

How long has thisbeen going on?

The fact that Microchip is using RISC-V has got to be nothing but good news for that technology, and Microchip---and bad news for ARM---and Nvidia.

They have never 'tooted their own horn'; just laid low and raked in the cash.

My favorite characterization of Microchip is "The largest microprocessor manufacturer in the world that you've never heard of".

How long has Microchip been aligned with---had an arrangement with---RISC-V?

[steelpillow]

Re: How long has thisbeen going on?

Most of their processors are PIC, etc. microcontrollers, which have hitherto had no need of vector processing. Their full-microprocessor products have tended to be ARM. With the increasing demand for graphics and AI on IOT/edge devices, there is a parallel requirement for microcontrollers to grow such capabilities. Down the line, RISC-V + vector* looks a good way to avoid ARM's license fees and occasional tantrums.

* Announcing the V-sweepstake: How many moons shall pass before the first commentard assumes that the V in RISC-V stands for "Vector"? First prize is the recollection that you read this post, all those moons ago.

[Tom 7]

Re: How long has thisbeen going on?

I think I read in New Scientist (12 Sept this year) that Nvidia are going to be using RISC-V cores in some GPUs. I can imagine using 32 bit cores to manage 64bit vector GPU work could be one way of saving power for 3D work.

[Bruce Hoult]

I really like this RISC-V Vector extension. It is one of two "vector length agnostic" vector instruction sets currently on the way between specification and machines normal people buy and use.

The other is ARM's SVE (Scalable Vector Extension). ARM also has more recently announced MVE (M-profile Vector Extension) for microcontrollers.

SVE and RISC-V V extension both give the programmer 32 registers of size that varies from machine to machine. Code is written in a way that doesn't have to know the actual register size, so one machine might have 128 bit registers, another 512 bit registers, and another (in future) 4096 bit registers and the same programs and libraries run efficiently on them all, without rewriting.

SVE allows for vector register sizes between 128 and 4096 bits. ARM's MVE gives the programmer 8 registers of always 128 bits each -- apparently SVE wasn't scalable enough.

RISC-V V (RVV) allows for register sizes between 1 element of the largest size handled (often 32 bits) and 2^31 bits. Version 1.0 of the vector profile for application processors (i.e. something that can run binary distros of Linux or similar) restricts the vector register size to be between 128 bits and 65536 bits. Those who are making embedded processors or supercomputers can choose register sizes outside that range if they wish.

RVV has a feature called "LMUL" that allows the programmer to trade addressable registers for register size. For example if your program loop only need 16 vector variables not 32, then you can use LMUL=2, use only the even numbered registers, and use pairs of registers as if they were a longer register. Similarly if your loop only needs 4 or fewer vector variables then you can use LMUL=8 and use only registers 0, 8, 16, and 24 but they are 8 times bigger than usual.

So a microcontroller with RVV might implement only 32 bit nominal registers, but if the programmer uses LMUL=4 then they get 8 registers of 128 bits each -- the same as MVE.

Both RVV and SVE are going to eliminate that awful situation where you have to rewrite all your SIMD code every few years when your CPUs move from MMX to SSE to AVX to AVX512 -- or a similar but shorter progression for ARM.

[Henry Wertz 1]

Scalable processor

Scalable proccesor -- just an FYI, they like to do this on ARM too. The typical phone, tablet, or etc. ARM has the MMU option, FPU option, NEON option, 64-bit ARM will have SVE, etc., but these are all technically options. Linux kernel requires the MMU; a few older ARM ports did support operation on FPUless chips, probably some of the software builds for wireless access points and NAS (Network Attached Storage) still have FPU-less ARM support (if a wireless access point is just feeding settings into a built-in wifi chip and running a admin web server, then this doesn't use any math and they can save a small bit by ordering an FPUless chip.)

I've heard good things about RISC-V! A modern design designed for simplicity but also designed so making high-performance versions is entirely possible; no royalties and designed to avoid various patents, no cost for one to do their own implementation.