Beagleboard peeps tease dual-core 64-bit RISC-V computer with GPU, AI acceleration, more for $119 If you’re looking for a modest RISC-V computer capable of running Linux, with AI and other acceleration thrown in, to evaluate the architecture, the people behind the BeagleBoard have teased such a thing: the BeagleV board, starting from $119 (£87). The single-board computer is the creation of three organizations: chip …
it goes against one of their core philosophies which is one OS to rule them all.Its why they didnt have a 64bit Raspbian (and still dont). The 64 bit Raspbian probably nearly doubles the amount of code to manage, a Risc-V would add another 50% or more.
I think I will be getting a few of these devices myself but they are in a different head space than the Raspberry foundation currently aims at, more Uni than school level.
The 64 bit Raspberry Pi OS (as it is now called) has been available as a beta for a few months and is fine, missing a few bits to be finished.
I've been using it for headless stuff since it became available, no problems.
The Pi has always been the most sorted and stable of the platforms for general computing tasks, whilst the Jetson Nano is the alternative if you need to use CUDA. All the other little wannabe Pi SBCs are just too flaky for my patience. I will grab one of these Beagle things though, give it a try. Probably won't be able to get hands on one until 2022.
Why should they?
Raspberry Pi's are enablers. They provide a common code base to allow you to interact and control things in the real world. And they are very good at it. If you have issues, there will be someone out there who can help you and it fits very nicely with their core market of Software/Hardware education
Despite that the boards are used for many other reasons, they have never been interested in cutting edge performance. Moving to a different architecture would give no benefit but create a whole load of support issues.
If you like and have the time to live on the bleeding edge, fine get a beagle. If you just want to pick up a building block for some project and don't want to spend hours recompiling to get some hardware or library to work, you are better off sticking with Pi
Pi's initial aim was education. That's also where RISCV came from. RISCV takes the FLOSS philosophy and extends it to hardware.
However, I doubt the Pi foundation has too much interest in switching architectures too hard with little short-term benefit and the loss of ARM economies of scale.
Pi rides on the back of Broadcom's TV CPUs: the big TV market reduces the chip cost to all purchasers. Eben Upton used to work at Broadcom, specifically on the GPU and video codec hardware. He was able to get a good quantity price for CPUs (and enough orders to sell that quantity). Over time he has shown Broadcom the value of proper GPL drivers.
The value to us licence religion extremists is as the driver source code is available anyone can maintain it (or hire someone else to maintain it) so Pi hardware can remain useful for years (8 so far). The value to Broadcom is that fanatical license extremists will select their products. The value of the hiding driver source code to chip designers is that they can decide to stop maintaining the driver whenever they want. This gives users three choices:
1) Some (eventually all) on chip devices become unusable.
2) Ever increasing time spent on software maintenance: back port security fixes to an old kernel where the drivers still work and deal with any software that depends on new kernel features you cannot backport without breaking the drivers.
3) Buy new hardware.
Nice sales every two years - but each time the chip designer loses 0.0001% of their customers because a few notice they can avoid that cost and hassle if they select a chip with a full set of GPL drivers.
While the RPi Foundation and Broadcom have a good relationship and Broadcom sticks with ARM, Pi's will remain ARM. Broadcom are likely to stick with ARM unless ARM tries a Softbank and tries to increase the license fees by an unreasonable amount (thank RISC-V that has not happened).
Best of luck to Beagle. I hope they get good quality GPL drivers and the CPU gets lots of other sales so the price drops.
So they can double the cost or a RISCV Pi for little in the way of additional performance?
RISCV provides massive cost savings to those using low power CPU's that are licensed (as it's typically ~1% of the cost of the CPU portion of the SoC - it makes a difference if you are shipping hundreds of millions of hard drives annually but not much of a difference for a few million RaspPi's annually) and potentially provides benefits for new and interesting CPU enhancements that are ignored by mainstream CPU manufacturers.
On the downside, the RISCV ecosystem will take a few years to mature to the level of the current Broadcom SoC ecosystem.
None of that suggests a move to RISCV would be beneficial. Short of a significant rise in ARM licensing costs (*stares intently at Nvidia*) the difference in pricing between an ARM SoC and a RISCV SoC are likely to be negligible (compared to the overall product cost) for products with similar capabilities and shipping volumes.
Or by interest do you mean compare the specs and continue to stay well ahead on price/functionality/performance?
I wish that the Beagle V was better, but for the price, what you are getting is only worth it if it is truly blob free.
The four USB 3.0 ports are provided by either a "GL3520 4 port USB 3.0 HUB (images of early PCBs)" or a "VL815 4 Port USB 3.0 HUB (images of current PCB)" chip. This may still offer more throughput than a RPi4, which is using a VL805 chip to push 5gbps USB 3.0 signalling over a 4gbps data bus.
+1 Beagle V ?
The video out can only support HDMI 1.4 1080p60, but the MIPI interfaces can support 4kp30 fps. The RPi4 supports dual 4kp60, and the hardware is technically HDR capable, just no software support (yet).
+1.5 RPi4 (higher framerate, and possible future support for HDR10)
Dhrystone Benchmark - Integer operation, rating in VAX MIPS aka DMIPS. The dual core 1GHz RISC-V U74 has a DMIPS/MHz of 4.27/2.5 (Best Effort/Legal). The RPi4 quad core 1.5 GHz BCM2711 has a DMIPS/MHz of 5.45/3.58 (64-bit/32-bit).
+1 RPi4 for integer maths
Whetstone Benchmark - Mainly floating point operation with overall rating in MWIPS. The dual core 1GHz RISC-V U74 does not appear to have a Whetstone Benchmark anywhere online ?!?!? The RPi4 quad core 1.5 GHz BCM2711 has a MWIPS of 2085/1883 (64-bit/32-bit).
+1 RPi4 for floating point maths ?
I wish that the Beagle V was better, but for the price, what you are getting is only worth it if it is truly blob free.
With all the PR bullshit and weasel wording on their crowdfunding site, it's quite unlikely this is the case. For a device that's supposed to ship in the next few months, either a statement stating open firmware (notably absent) or a GitHub link would be expected.
There is a github, which has a schematic (with blurry images), block diagrams and a full bill of materials: https://github.com/beagleboard/beaglev
No firmware there though.
I note they were very careful to state open hardware (schematics etc.) and open software (presumably some kind of Linux) but they specifically avoided saying open firmware. That raises my suspicion at this point, especially since I have been completely unable to locate any firmware online for any device with the U74 cores.
I was going to mail them to try to get some clarification, but there seems to be no contact link, and that heightens my suspicions further.
If it's not completely 100% free of binary firmware I see no reason to replace my well-supported Raspberry Pis. Especially not for over £100 each.
Jason Kridner
BeagleBoard.org Co-founder
Email: jkridner@beagleboard.org
Webex: Jason's meeting room
Telephone: 713-234-0535
That was easy ... also there are still loads of pi driver firmware that is proprietary....this is still an awsome thing ... from TaloSpace
---"on the the other hand this might be a truly open system based on the fact that the Freedom E300 and U500 series are open scource under the Apache licence.While some parts of SiFiveare propietary, this line is not, and we presume that the U700 series will be like wise.---
https://www.talosoace.com/2020/09/the-first-production-risk-v-workstation.html
you must try harder grasshopper
Id have one to complement my bbb arm cortex a 8 rev c, and then all i need to do is learn to use C in anger
I wonder why the contact info was nowhere to be found on the funding site. Regardless, might drop a line and see what the plans are.
The RPi is a very closed system, which is why this one would need to be open to make dealing with it worthwhile both in hardware cost and software support. I have no interest in rip and replace, one closed system replacing another closed system, but opening things up would potentially be worthwhile.
Ok, so it's not as good as the RPi is, but remember that this is a first generation product. It was never going to be.
If you want there to be a credible alternative to ARM (really NVidia in a dress), you have to accept that isn't going to spring up overnight, and that the first releases ain't gonna be perfect.
I'm not even an Open Source evangelist, but even I can see the value in a totally free hardware ecosystem (and yes, I know there are doubts about blobs etc on this, but baby steps). Competition breeds innovation.
I am reading through the risc-v spec on the webiste. It uses the same opcode mnemonics that I saw on the Prime computers, so LH and L for load Half and full register. I also missed the quad floating point on Prime, but this has been thought of. The Prime instruction set was also called 32I, because immediate mode was invented. It is very encouraging.
What's wrong with my thinking?
RISC-V isn't so much a brand new architecture as a convergence of similar architectures into one standardized form. I've used at least four of these processors, all with slightly different architectures, but they all have the same regular set of registers, reserved registers for compiler function linkage and the like three address instructions with all memory accesses through indirect instructions. There are detail differences such as the location of the exception vectors, number and access to special registers and cache layout and operation, cache and data bus layout and operation but they're all very much of a muchness. -- you've seen one, you seen 'em all.
An interesting question would be why there are other architectures. Really complex instruction sets like the x86 are really emulated in microcode and alternatives like the ARM aren't that different (its main difference appears to be conditional instruction execution, the idea being to save time lost in refilling the pipeline because of jumps, but I'd like to see how much this type of instruction is used in practice.
ARM has deprecated conditional execution on 32 bit and never had it on 64 bit ISA.
The U74 core treats a conditional branch over a single instruction, and the following instruction, as a kind of predicated execution with no pipeline flush no matter which way the branch works out.
I'm still rather miffed that OpenRISC never got even a fraction of the attention that RISC-V got, even though OpenRISC is a fully open project, instead of just an open ISA specification like RISC-V.
RISC-V has commercial interests behind it, while OpenRISC was (is?) truly the 'open hardware' spirit. In that light it's galling to see all this excitement about RISC-V when it doesn't really bring anything new to the table which Arm isn't already doing, or IBM with OpenPOWER.
Now a board with an OpenPOWER CPU on it... that might be interesting.
I never understood the RISC-V hype train either. A bunch of embedded, incompatible CPUs that seem more applicable to hardware like nVidia's Falcon units or embedded disk controllers? I had OpenRISC on an FPGA many years ago, fond memories but cheap ARM chips displaced the need over time.
Now a board with an OpenPOWER CPU on it... that might be interesting.
That would be awesome. I'd buy several, if they managed to be as open as the IBM offerings.
> Now a board with an OpenPOWER CPU on it... that might be interesting.
Then you would be very interested in the next libre-soc ( https://libre-soc.org/ ) . They were trying to implement some very innovating ideas (from the 1960's) by developing alternative extensions for the RISC-V, but ran headlong into issues* with the RISC-V Foundation. And are now using the unpatented innovation of Seymour Cray's CDC 6600, and plan to implement the ideas on OpenPower architecture with the blessing of IBM.
* https://www.crowdsupply.com/libre-risc-v/m-class/updates/nlnet-grants-approved-power-isa-under-consideration (This bit about the EU Commission is interesting as well, https://www.crowdsupply.com/libre-risc-v/m-class/updates/openpower-eula-released-fosdem-and-more ).
They are releasing a risc-v ( https://www.crowdsupply.com/libre-risc-v/m-class/ ), but they are also working on their new OpenPower scoreboard SoC (powerpc64).
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