Start trek, the next generation: PCie 4 flash controller demo flaunts speedy peripheral vision An SSD controller company has demonstrated faster SSD access with a gen 4 PCIe controller that was twice as fast as gen 3 PCIe. Fore! PCI Express 4.0 finally lands on Earth READ MORE Taiwanese flash controller firm Phison - which demo'ed the tech at trade show CES in Las Vegas last week - said desktops and notebooks could …
Agreed, but if you're on a mainstream Intel desktop chip with only 16 PCIe lanes available, having the speed of those lanes doubled effectively gives you the same speed with twice as many lanes. Once you have an NVMe SSD (x4), a modern GPU (x16) and some spares for the chipset IO (x2 or thereabout), you've used at least 22 of your available 16 lanes and will have to rely on a PLX chip, which will be a bottleneck. AMD having 20 lanes on their desktop platform somewhat alleviates this, but a doubling in speed would still be beneficial.
The motherboard just has wires from the CPU socket to the PCI-e slots. Some existing motherboards will be able to work with PCI-e 4 because their traces are of sufficient quality to carry the signal, but it is unlikely that they will work with PCI-e 5 as that will be an even harder signal to carry.
From Wikipedia
For single-lane (×1) and 16-lane (×16) links, in each direction:
v. 3.x (8 GT/s): 985 MB/s (×1) 15.75 GB/s (×16)
v. 4.x (16 GT/s): 1.969 GB/s (×1) 31.51 GB/s (×16)
v. 5.x (32 GT/s): 3.938 GB/s (×1) 63 GB/s (×16)
GT/s is gigatransfers per second, these are informal language that refer to the number of operations transferring data that occur in each second in some given data-transfer channel. So only a bit meaningless.
PCI-E v5 has only just started to be worked on, I would imagine it will 3 or 4 years before it turns up.
>PCI-E v5 has only just started to be worked on, I would imagine it will 3 or 4 years before it turns up.
PCI-e 5.0 has been being worked on for quite a while, it is being finalized this year and we should start seeing PCI-e 5.0 products next year.
PCI-e 4.0 was delayed which is why it feels like 5.0 is coming out so soon after it, it was expected that many OEMs would skip PCI-e 4.0 (although PCI-e 5.0 devices will be able to fallback to 4.0).
For reference an 8 lane card on PCI v3 would have c8 GB/s of bandwidth, however M2 only comes in 4 lane so is maxed at 3.8GB/s.
As previously mention, the paltry number of channels providded by CPUs manufactourers is teh real bottle neck, i just don't understand why Intel specifically is so mean in this area, especially on their top end processors.
This will have a nice improvement for servers, but also a nice boost to notebooks using the Thunderbolt connector. One more doubling of TB bandwidth would make the difference between using an external GPU box and an internal card nonexistent. External drive arrays for the video editing audience will also notice a nice boost connected to mobile workstations. And of course docking stations overall can become more elaborate with a single power and data interface that drives whole office setups too. In the desktop arena you might well see a number of cards that needed x4 connectors in the past, able to deal with just and x1 connector under 4.0. That may well help SFF systems to become more capable too.
Who needs it? Oh wait...
There are apps with an ~insatiable appetite for ram, and many more would code for if it were mainstream.
Dram is expensive & a bit thirsty.
We can page memory overflows to storage to give an illusion of large memory, but historically, there is such a chasm between memory and storage speeds, it is of very limited use.
Yet when the possibility of storage arrays almost as sequentially fast as memory of not so long ago arises (i.e. ~unlimited, cheap ~memory), its a giant yawn apparently.
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