Three's company: Micron intros first 3D and triple-level cell SSDs

Micron has announced its first 3D NAND SSDs, triple-level cell (TLC pr 3bits/cell) 1100 and MLC 2100 products. Intel, its flash foundry partner, introduced its own 3D SSDs, MLC (2bits/cell) ones, in March with the DC P3320 and P3520, with maximum capacity of 2TB. These had an NVME interface whereas Micron’s 1100 has the slower …

[Known Hero]

biding my time

For real world benchmarks. Although loving the specs :)

[chris 17]

How much?

did i miss the price in all that bumpf?

[diodesign]

Re: How much?

No prices yet - they're not on sale for another month or so. The article even says so in the final paragraph.

C.

[Anonymous Coward]

Am I the only one...

... who just keeps suffering and can't adapt to the malformed nomenclature, no matter how many times it's repeated? FFS it's not triple-level, it's triple density. Or octuple-or-what-ever-level, if you insist talking about the number of levels. Or quadruple if you want to talk about the relative number of levels. In fact the only description that makes absolutely no sense at all IS TRIPLE-LEVEL EXCLAMATION MARK.

I know, it's about 15 years too late now but still... hence the question. Am I the only one?

[JeffyPoooh]

Re: Am I the only one...

Nope. We had this discussion a couple of weeks ago (triggered off by bits vs levels error).

The subtle issue is that if eight level, three bits per cell are called 'triple level', then the technology may stagnate until they can achieve 16-level, four bits per cell to be misnomered 'quad level'.

In fact, they shouldn't overlook intermediate approaches with non-power-of-two levels and fractional bits.

Bad naming reveals poor thinking.

Your point is valid.

[JeffyPoooh]

Re: Am I the only one...

Here...

http://forums.theregister.co.uk/forum/1/2016/05/20/the_changing_phase_of_storageclass_memory/

Misnomer -> TLC or triple-level cells

Since it's 3 bits per cell, it's actually 8-level cells ("8LC"). It's not 'triple level'.

The fact that somebody misnomered "TLC" and "triple level" is clear evidence that they're not thinking clearly.

I hope that they realize that they don't need to stick to levels in power-of-two steps, and they could actually use honest Triple (3) Level Cells (3 states per cell), giving 1.585 bits per cell. Yes, it'd need a digital circuit to organize the bits. Perhaps easier than struggling with 8-level analog circuitry. Trade off of course, finicky circuit and speed vice density.

Breaking away from power-of-two thinking will become essential for the next step. 10LC is a good next step on the way to 16LC (four bits per cell).