Press Release as article?
Disappointed.
If high-speed AI inference is what you’re after, memory bandwidth is the bottleneck to beat. At a mind-numbing 21.6 petabytes per second (PB/s) of memory bandwidth, Cerebras' dinner-plate-sized AI accelerators were already 1,000x faster than Nvidia's or AMD’s best GPUs. The chip newcomer unveiled its next-gen Wafer Scale Engine …
Still trying to get around the concept of compute power as KW. The only way I can relate to electricity consumption is kettles.
Hence each backpack is taking 40+ kettles. Unless we dual purpose them as water boilers just think of the cups of tea that's displacing every few minutes. And how to pipe boiling water to the IT department or do we inject the tea leaves in-rack?
Oh I forgot with all that AI power you don't need the department. Takes the biscuit!
Given how we mostly make electricity by boiling water and pushing it through turbines, I have often wondered if there's mileage in making these things run deliberately hot - just hot enough to maintain boiling temperature at the other side of their cooling loop - and try and recover some of the electricity.
I'm sure it's technically possible - just haven't bothered to do the maths on if it would be in any way practically useful.
Barely-steam is barely worth having, by the time you've moved it to where you want it, it's just hot water. The steam you want for turbines is scary stuff, not the slight fog that hangs around at the top of your kettle. 600oC and 250 Bar, compared to 100oC and atmospheric already...
Silicon's already starting to get leaky at 100oC, and SiC and GaAs and friends which are happier running hotter don't seem to be contenders for massive integration, despite being pretty speedy. (I just paid a few hundred bucks for a single xor gate, that's no way to build a supercomputer these days)
It's a bit like measuring fibre capacity in "tonnes of glass". It's meaningless except to the parasite industries queuing up to build the slop factories as they buy substation transformers that could otherwise supply a large town or a small city, pushing up prices and lead-times for utility companies, and pushing up interest rates as they gobble up all the credit that could otherwise be lent to smaller or more productive businesses
I love this approach of upcycling leftover unsold WSE-3 kit rather than tossing it like salad plates chipped beyond repair. Those still brand new wafers are clearly more capable than previously thought, by 2x, so yeah, upgrade their power delivery and heat removal hardware subsystems to the hilt, and support running them twice as fast I say -- way to go! (no need whatsoever to junk-pile them on the growing trash heaps of superfund landfill sites because some dubious newer SKU replaces 'em ATM, imho!)
Plus, that steampunk backpack they've designed for this looks right made for the part, though at 100 pounds ("The Next Platform" TFA link) it may yet challenge a few GhostBusters and stylish goth waifs alike (eg. on maneuverability). It's nicely modular and makes CS-4 1.5x denser than CS-3 iiuc, which is a bonus as you then get 3x the oomph per square foot, saving on related square dancing, line two-stepping, punctual clogged waltzing, and whathaveyounuts useful cartesian space (ditto cubic boot scooting afaik).
WSE-4 heaven can wait a bit (for believers) and'll hopefully sport all the sultry extra SRAM everbody prays for. FP64 dataflow capabilities for HPC would be nice too, though MI430X is now slated to crank 288 TF/s there (albeit non-dataflow), that seems hard to beat ... maybe maverick-2? ;)
SRAM cells basically ceased to scale in the most recent process generations, which is probably part of the reason why they are still on N5 - there is zero shrink of SRAM cells with N3 even though logic cells see a decent shrink. N2 gives you a bit but the juice (in the form of per wafer cost 3x as high as N5) is probably not worth the squeeze for that type of design.
What they MIGHT do, and AMD's partnership hints strongly at it, is stack an entire wafer of SRAM on top of a wafer of compute. They could use all the area currently consumed by SRAM on their main wafer for more compute, and shrink that to N2 where it gets some benefit, and then stack a wafer that's entirely and solely SRAM made on N5 on top like AMD's 3D cache. While that stacking is TSMC's technology so anyone can use it, it complicates the design in certain ways (gotta make room for all the TSVs) and AMD's experience with that would probably benefit Cerebras.
I don't know exactly how much SRAM you'd get if you filled a wafer with nothing but, but safe to say it would be several times more than the 44 GB they have now.