Architecture is the trivial part. A working ISA and a reference microarchitecture is something a competent group of postgraduates can produce in twelve to eighteen months. RISC-V has demonstrated this several times over. The hard problem starts the moment you want that design realised in silicon that runs at multi-GHz, hits competitive perf/watt, and yields at acceptable rates. That is a 15-to-25 year industrial project, not an engineering project, and nobody in the European policy class is treating it as such.
Look at the actual supply chain. ASML ships the lithography, Zeiss does the optics, Trumpf does the lasers, so the EU owns the most jealously guarded link in the chain. Then count what has to arrive at the fab loading dock alongside the scanner: photoresists from JSR, TOK, Shin-Etsu (Japan, near-monopoly at EUV-grade); ABF substrates from Ajinomoto (single-sourced, Japan); silicon wafers split between Japan, Taiwan and Korea, with Siltronic in Germany as a partial European foothold; deposition and etch tools from Applied Materials, Lam, TEL; metrology from KLA; test from Advantest and Teradyne; EDA from Synopsys, Cadence and Siemens EDA (the last is nominally German but the engineering and tool chain sit in Texas). High-purity gases and specialty chemicals are one area where BASF, Merck, Linde and Air Liquide are genuinely strong. Almost everything else in the bill of materials is American or Japanese, with Korea and Taiwan filling in the rest. You cannot build a 5nm-class fab on European soil today without permission from at least three foreign governments, and that permission is conditional on each of those governments not having a worse week geopolitically than you do.
The TSMC Hsinchu and Tainan clusters did not happen by accident, and neither did Silicon Valley before them. Geographic co-location of fabs, gas plants, chemical suppliers, mask shops, packaging houses and test floors compresses iteration loops from weeks to hours, lets tacit process knowledge diffuse through job mobility, and means engineers can physically walk over to a supplier to diagnose a yield excursion. The EU response so far has been to drop individual fabs into politically convenient locations: Intel Magdeburg (now stalled), ESMC Dresden, a smattering of STMicro and GF capacity in Crolles. That is a press-release strategy, not an industrial one. The correct unit of planning is a semiconductor city: a designated region with multiple fabs, on-site gas separation, chemical synthesis, wafer reclaim, mask writing, packaging and test, with housing and a couple of polytechnics tuned to feed it. Build two or three of them in different member states, not one, so process knowledge competes and diffuses, and so a single fire or flood does not take out the continent (see the 2021 Renesas fire and the Texas freeze for what single-site dependency actually costs). Different states can take different segments of the chain before sustainability: Germany already leads on chemicals and optics, the Netherlands on lithography, Belgium on research via IMEC, France on materials and on the STMicro design base, Italy and Ireland on packaging and assembly. The Chips Act spreads €43bn like jam across a slice of bread, when what it needs is to be poured into two or three industrial clusters and left there for thirty years.
Yield is the other thing the policy papers do not mention. A new process node typically starts at 30 to 50 per cent yield and takes two to four years of relentless line-side engineering to reach the 80 to 90 per cent needed for economic production. That learning is institutional, embedded in thousands of process engineers, equipment technicians and integration leads, and it does not transfer in a PowerPoint. TSMC's lead over everyone else comes from yield engineering culture accumulated since 1987, not from any single piece of kit on the floor. Replicating that is the actual problem. Buying ASML tools is the easy bit.
In the meantime, a sovereign architecture absolutely can run, today, on FPGA fabric. Xilinx and Altera silicon is still American, so this does not close the underlying gap, but it decouples "who designs and audits the chip" from "who fabricates it" while the latter is being built. Performance will be five to ten times off an ASIC at the same node, worse for memory-heavy workloads, but for sovereignty-critical use cases (HSMs, root-of-trust controllers, regulator-grade compute, certain classified workloads) that gap is tolerable. It also gives you a working software stack, verification flow and toolchain that ports onto your own silicon the day it ships, which is the asset an ISA-only programme cannot produce on its own.
The reason none of this gets discussed properly is that it is a 15 to 25 year programme requiring co-ordinated industrial policy across a dozen member states, sustained capital allocation through six or seven political cycles, and public acceptance that the continent will not be competitive on leading-edge logic for at least a decade after starting. That is unsellable in a five-year electoral window, so instead we get "European RISC-V initiative" launches and call it strategic autonomy. Picking an ISA is the part of the problem you do when you have run out of useful things to argue about.
