Way to go
Yeah, Intel incorporated FPUs into its CPUs (486DX, 1989), AMD integrated the IO-MMU in there (2007), they (and competitors) later integrated many cores in-package, io-controllers, GPUs, vector units (and matrix, and NPUs), and to some extent NoCs ... the trend has definitely been towards combining ever more functionality that was previously realized through distinct external units, into increasingly sophisticated integrated packages.
NoCs and in-package Networking (with DPUs, SerDes galore, and associative memory) sure sound like the next thing to integrate, especially with CPO, to deal more seamlessly with, both, the increasing number of in-package cores, and many similarly packaged external units in a system, plus myriad other devices (pooled memory, storage, etc...), imho.
It seems to me that the current rack-scale approach where scale-up requires external switches could largely do away with those by using in-package networking chiplets, a bit like the last 3 diagrams here (based on POWER9⁴). And if IBM was using POWER10 CPUs as switches 3 years ago, I'd imagine that similar tech could readily be integrated via chiplet(s) in a contemporary CPU/GPU/switch highly modular combo device that is easy-and-economical-to-deploy-and-scale.
The perf-per-watt efficiency enhancements of going rack-scale could see a further uplift with this sort of tech I think ... (maybe?)
⁴⁻ still waiting anxiously for POWER11, and now POWER12 too!