AMD bets on rack-scale compute to boost AI efficiency 20x by 2030 With Moore's Law on its last legs and datacenter power consumption a growing concern, AMD is embarking on an ambitious new goal to boost the energy efficiency of its chips 20-fold before 2030. And it sees rack-scale architectures as a key design point to get there. "The counterintuitive thing here… is the bigger the device, …
I like this 20x30 goal as a follow-on to AMD's previous 30x25 and 25x20 objectives.
Much as El Capitan is 4x as power efficient as Fugaku at dense-matrix HPL in Top500 (rather than 30x), I guess we won't see a 35 ExaFLOP machine in 30 MW by 2030, but even 5 or 6 ExaFLOPs in that power envelope would be nice, and 10+ FP64 EF/s in 40MW would be even yummier!
Fair enough. I was attempting to get something more realistic than AMD's optimistic 20x by 2030 goal.
For example, looking back at Top500 in 5-year chunks, through Jaguar, Titan, Fugaku, and El Capitan, suggests improvements in perf/Watt that decrease over time, from 8.5x (2010-2015), to 6.7x (2015-2020), to 4x (2020-2025). That's where my 4x for 2030 comes from (with some optimism; plus, that'll make it approx. 1000x from 2010 to 2030, which is nice!) ...
Just saw this report from Anastasia In Tech - there is definitely some logic behind this.
Very impressive tech. Given that yours truly started with electronics when the idea of sticking transistors in ICs had just taken hold we've travelled a long way.
Yet, personally I don't think we're anywhere near the end of interesting ideas..
I wish you all a good weekend.
I suppose it depends upon how/what you define as efficient.
From where I am sitting, and bearing in mind the environmental need to reduce the use of energy in the future, the colossal quantity of energy that is likely to be consumed by these so-called advances doesn't look terribly efficient at all.
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