Trump official warns they're putting the squeeze on CHIPS Act winners Chipmakers waiting on billions of dollars of CHIPS Act funding should be prepared to return to the negotiating table, US Commerce Secretary Howard Lutnick suggested during a Senate hearing this week. The $53 billion funding bill, which sought to reinvigorate domestic semiconductor manufacturing, has been a point of contention …
PErhaps Drumpf might like to sort out the hygene at his Bedminster Golf Resort. It has been judged to be the worst place in Somerset County, NJ to eat.
Hey Donnie, do you want some CHIPS with that unhygenic buger?
Seriously, Drumpf has always been bad at running a business. Ruining a business, is his forte. He's running the USA into the ground just to make a fast ten billion bucks for him and his family.
So, what happened to bringing manufacturing back to the US? Yeah I know that several IC manufacturers are expanding their presence in the US but this started well before Trump regained the "throne" and of course he wasted no time taking credit for it.
By creating uncertainty on whether they'll get the money they've been promised some of them might change their plans. I'm sure he'll find a way to blame that on Biden even when it will be clear it is via his own actions.
This (along with his string of bankruptcies) is why he was no longer able to build any buildings himself but was reduced to licensing his name in the last decade or so before he became president the first time. He struggled to get contractors to work with him because he sees every deal as something that can be renegotiated anytime he chooses, but if the other side tried it he'd sue them in a heartbeat. If I was say a major plumbing contractor in a big city and I knew one guy in town had a reputation for trying to change deals after contracts had already been signed, when he was soliciting bids I'd throw his RFP in the trash without even looking at it.
"A single wafer can contain anywhere from a few dozen chips to several hundred, depending on their size and complexity."
For advanced CMOS processes (30cm) wafer, for all but the real 'monster' die one would expect thousands of die on the wafer.
https://www.silicon-edge.co.uk/j/index.php/resources/die-per-wafer
e.g. AMD Zen 5 CCD is 70.6mm² so guessing that to be 8.4mm x 8.4mm. This would give 856 die per wafer. So simpler devices will be into the thousands. As for all the 'jelly bean' components (regulators, PMICs, simple logic ICs, audio amplifiers, etc etc, ("jelly bean" parts) that get pumped out in the millions that have a die size typically of a few square mm probably tens of thousands on a wafer.
Do ya want a REALLY REALLY BIG BANG FOR YOUR BUCK? How about worldwide FREE and completely Open Source?
Friday, June 6, 2025
NCA (North Canadian Aerospace) of Vancouver, British Columbia, Canada is pleased to make a pre-announcement of their upcoming 256-bits wide combined-CPU/GPU/DSP/Vector super-chip running at 10 THz clock speed made using multi-head electron-beam and laser-based Copper Powder Deposition and Sintering on Borosilicate glass substrates. By increasing the line trace widths and depths into the multi-Micron range (i.e. 60 microns wide at 100 microns deep!) and upping the voltage to 5 Volts, large scale increases in pure number crunching power have been realized within a 3D-stacked array of Borosilicate microcircuit dies that can be etched and 3D printed at your own office or home environment using common-off-the-shelf (COTS) components, materials and 3D printers.
The fully-ITAR-free chip Designed and Made Entirely in Canada is optimized for 3D printing within home/office/commercial environments for any person or company who downloads the tape-out design. We ensured that the final chip is optimized for low-cost of materials and to facilitate application-specific production runs without restriction as the end-user is able to easily modify the tape-out designs via the downloadable enhanced automated circuit design application toolset. We have also facilitated circuit production within non-optimal industrial conditions so as to allow DIY (Do It Yourself) microcircuit printing within home, office and commercial sites where high-level clean rooms are simply not available.
By using spectral domain processing techniques that use comb filters to bring optical frequencies down to the 10 Terahertz range, we are able to get a STABLE clock rate that is used for the on-board processing block synchronization, optical communications clocks, software defined radio (SDR), general purpose analogue and digital I/O ports, high-speed-capable global navigation system and other high-speed onboard sub-systems which will facilitate end-user-directed on-chip feature sets and allow for end-user-defined application-specific microcircuit inclusion on any final 3D printed super-chip product.
The following set of features is included within the tape-out super-chip design:
256-bits-wide Combined-CPU/GPU/DSP/Vector Array Processor with 4096 hardware processing cores at 16 virtual threads per core for 65,536 total threads running at 10 THz clock speed sustained for 256-bits wide Floating Point, Fixed Point and Integer arithmetic.
The entire chip tape-out design is 3D printed on layered stacks of 200 mm by 200 mm by 3 mm thick Borosilicate glass plate dies using multi-head electron-beam and laser-enabled copper powder-deposition and sintering techniques that create line trace widths of 60 microns wide at 100 microns thick running at 5 volts for optimal clock stability and for mitigating RFI/EMI, crosstalk and inductive loads.
Individual Borosilicate glass layer dies are stacked vertically and interspersed with dialectric cooling plates that are 5 mm thick hollow-tube-etched ceramic plates for fast thermal transfer capability, and each cooling plate is filled with silicone oil rapidly circulated in and out of each plate for best cooling of the above and below CPU die layer. An entire super-chip can be 3D printed at home in less than 72 hours for a per-unit cost of less than $300 CDN ($250 USD) which has number-crunching performance that surpasses every current 2025-era T500 supercomputer system on the planet!
This type of super-chip microcircuit die construction allows for working super-chips to be 3D-printed at home or in your office using common 3D printers that have micro-particle copper powder deposition capabilities. We use nano-powder-based dopant deposition and diffusion techniques plus a further application of high-heat resistant dialectric ceramic powders to get the semiconductor and insulator portions of the circuitry done correctly. Much smaller CMOS and GaAs substrates are supported and those tape-out designs will be released soon after which can use common photolithography and chemical etching techniques to shrink the high-performance die layers down to a few square CM in area.
If you need a working design for a 300 mm by 300 mm working area 3D microcircuit multi-head e-Beam and Laser Etching/Powder-deposition/Sintering printer able to make this super-chip at your own facilities, we have that design too available for you to download for free along with our in-house designed and coded EDA (Electronic Design Automation) software tool set which also has advanced 2D-XY and 3D-XYZ circuit design and simulation along with CAD/CAM/CAE/FEA as part of the software tool set!
P.S. They Lied! It's really a 256-bit wide at 10 THz superchip and not a mere 128-bits wide! And it's a heck of a lot more than 50 PetaFLOPS sustained!
Intel, AMD, ARM, Qualcomm, Huawei, Samsung, TSMC, IBM are soooooooo Royally Rottenly Screwed and Toasted in the next few weeks!
V
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