Chip designers latest casualties in US-China trade war In the latest assault on China's burgeoning semiconductor industry, the Trump administration has erected new curbs on the sale of chip design software in the region. "On May 23, the U.S. Government informed the Electronic Design Automation industry about new export controls on EDA software to China and Chinese military end …
It’s counter-productive and forcing China to re-engineer and do the work themselves and gain independence and gain strategic technical know-how. See how the US could not hope to ever make an iPhone - never mind the price.
I’m sure if the UK Banned Coke and Pepsi the result would be Barr’s, Panda, Virgin and Supermarket own-brand Cola would evolve to fill the vacuum.
No they won’t.
Chip EDA software is some of the most clever and IP-intensive software on the planet. And by IP, I don’t mean “people know what it does, but you aren’t allowed to copy it”, this is classic “trade-secret: it’s just better than anything you have, how it does what it does is unknowable, but it just is”. This is not at all like software compilers.
Open-source equivalents exist, written by professors with 30 years experience in the field for their students. The output of those are chips which are many times more power-consuming and silicon area than the proprietary versions.
Chip EDA software is the un-sung equivalent of ASML photolith, and is *far* more strategic and harder to catch up to.
China has many talented and clever people. And of course “never” is a long time.
But what I’ve told you, is that the best of MIT and CalTech, are currently 20 years innovation behind Cadence etc. One of the reasons for that, of course, is that when bright young PhDs and mid-careers at MIT come up with potential good new ideas, worth investigating Cadence offer them million-dollar joining bonuses, along with million-dollar salaries. And that’s the same whether they live in China or USA.
Chinese companies will take 15-20 years to catch up.
Plus there are other strategic issues to navigate. Like getting tight-coupling with TSMC libraries and design rules, which are their IPx. You can’t just sit with your head down, tap furiously on the keyboard, and magically expect to close these gaps.
Oh you have, and it's always out by an order of magnitude.
China has over 40 million people attending university while the US has under 12 million.
Also the American education system is a bit weird and has been for a long time. There's a video online of Feynman giving a lecture to MIT freshmen and I was really shocked, he was teaching university students stuff (thermodynamics) that I was taught at 14 or 15 in an ordinary UK school.
The stereotype that the Chinese only copy and do little original work was never true and is far less true now.
I predict in a decade or so it will be China restricting technology exports to the US.
Then you very much read what you thought I was going to say, rather than what I actually said. Nowhere did I say that China was only good for copying.
Most of my business is in the Asia Pacific region, I speak Mandarin, have a lot of respect for both Chinese engineering, and way of doing business.
What I *said* was that in the field of silicon EDA software, Cadence and Synopsys have spent their time and money solving hard problems, are now being rewarded for having done so. They are decades ahead. You can’t just catch up with the magic wand of waving a million graduates at the same hard problems from cold. They’ll have to work the solutions out the long way, like Cadence and Synopsys did.
Was I replying to you?
Did I suggest you were expressing the stereotype?
Once one person has worked out how to do something, it's much easier for someone else to work out how to do it as well. Just knowing it's possible and having a broad overview of the process could cut the research and development time by a huge amount.
As a general rule, you’re right. That applies to rocketry, TVs, lithography, and business processes. Much of innovation is researching a dozen plausible good directions, most of which turn out to have their own issues. Once everybody knows not only that which idea works, but exactly how good it is when working properly, and has a 3x return on investment if you develop it, progress by others is usually quick.
It does *not* apply to the statement “various algorithms and heuristics exist which can combine physical synthesis, place-and-route algorithms, detailed transistor models from silicon vendor, parametric IP models, IR droop modelling; to produce outputs which consume less than one-third the power of the naive version; and which have a 95% yield on vendor process rather than 70% yield”.
This tells you *nothing* about what those algorithms and heuristics might be.
It depends on their target, if they want a commercial system to equal that of the current systems you describe then they will encounter serious problems. If they just want something that is "good enough" then they should be able to get something that "more or less" works. Expensive, possibly slightly less powerful chips are better than no chips. And they can always just throw more chips at a problem so a minor performance deficit is easy to overcome.
Also when you control the raw material supply, high yields while desirable are not essential. China has a huge advantage in that regard: If their yield is 50% of the western alternative but the costs are only 50% of the western alternatives then while wasteful it's economically a comparable result.
Chinese costs aren’t randomly lower, for stuff like chips. That’s an EU delusion that somehow the Asia Pacific bad men are undercutting you on cheap labour and cheap raw materials.
TSMC Taiwan costs are lower than EU and USA *because* their yields are higher, *because* their industrial quality process and approach is better.
Labour costs are not a major part of chip fab cost. Labour is a major part of chip fab construction- and if you ask Morris Chang why USA foundries are intrinsically expensive, as many have done, he will freely tell you that US construction labour force is poorly skilled, uncooperative and entitled, very slow unproductive per hour, poor quality (high amounts of rework). You can dismiss his view if you like, but he does have the overview of having done both countries, founded and run the most successful fab on the planet,and trained and worked in USA (MIT and Stanford)
You can’t economically make chips at 50% yield and make it up in volume,you just can’t. And China isn’t stupid enough to try, nor weak enough to need to. It will trade its way to success.
I wasn't just referring to labour costs. China can source the raw materials for a lot less, the fabs can be built for less, the energy is cheaper, they wont have to pay millions for the software. Maybe it won't be a 50% reduction but I also doubt if the yield would be as low as 50% - maybe 75% yield at 75% of the cost is more likely.
China produces 75% of the worlds raw silicon. China is the leading producer of boron. Of course they can get the raw materials for a lot less than they sell them to western producers and they can cut off the supply to the west if they want to. We'd still be able to source them from other suppliers but that would cause the material costs to skyrocket, also many of the other suppliers are aligned with China or Russia so supply from them is not guaranteed if China stops exporting..
It'll take them a few years but not the 15 to 20 you suggest to produce functionally and financially similar devices to western fabs.
You can’t economically make chips at 50% yield and make it up in volume,you just can’t.
Of course you can, you just build 2 fabs or bigger fabs.
Testing is done on wafer so getting some duff chips is not a critical issue and is expected. It's not like they'd be dumping fully packaged chips so the losses from reduced yield is not a major problem.
You're really talking about layout modules, figuring out the floor plan. This is a complex, non-deterministic, task but it really involves a lot of Monte Carlo like simulations with a fair bit of know how about secondary design considerations like signal timing and noise. I've only had peripheral contact with this, first through actual logic design 'back in the day' and more recently with FPGAs, but the general rules are still the same. There's a lot more to designing logic than just stringing gates together when you get to the margins of device performance.
This level of technology can be a bit tricky but you'd be surprised just how many really clever buggers there are out there -- and a whole bunch of them are Chinese. I've worked with quite a lot of them and I would never count them out. Go into any R&D group or research lab and you'll find a significant part of the workforce are Chinese origin, especially on the West Coast.
The general rules for modern ASICs are *not* the same as FPGAs. It’s a whole different ballgame.
How long did it take you to close timing and P&R an FPGA - a few days for one person? Using tools that came free with the FPGA.
Would you be surprised to learn that the answer for a modern SOC *given the Verilog source* to get to a mask handoff, takes a team of 200 specialists 6-9 months, costing $200M+. In tools terms, the team will be using licenses ranging in price from $50k per seat per year, up to $2.3M per seat per year for one of them. The Design Rule Checker alone may be validating 10k+ rules on a 3nm-class process.
What it took you to do the job in the 1990s is not in the same class as 2025. That’s *exactly* what I mean when I say that Cadence and Synopsys are 20 years ahead. You are quoting the 1990s job, and free tools exist for that. But the complexity and sophistication of what needs to be done, has been exponential.
The downvotes on Justthefacts posts on this topic just go to show how much people really do not understand Silicon, Silicon-IP and EDA.
EDA software is not shrink-wrapped, EULA click one shot software. It was one of the first markets to move away from perpetual licensing and into time-based/subscription models. And it comes with massive levels of field support.
No EDA? No chips. It's that simple.
China will create to fill the gap. They have to.
> Open-source equivalents exist,
And now there may be more soon-ish.
The real problem, of course, is that all the good eggs are stored in very few baskets, any of which can be controlled by who knows whom slightly less than completely. If tomorrow HR duckfaces and their pets at Microsoft happen to act up, wipe out all up-to-date code and torch the backups “in protest against mistreatment of Spirit Whales”, nothing of great value will be lost. But what if this happens in Siemens?..
> written by professors with 30 years experience in the field for their students.
In which field? Being professors, writing software or actually designing chips?
> The output of those are chips which are many times more power-consuming and silicon area than the proprietary versions.
When it turns out Siemens is not like Microsoft. Yet.
Professors of chip design……
What the open-sourcies fail to realise, is what an academic actually *is*. A professor needs to know enough to lead a *graduate student* to write a PhD thesis. They’re first-line managers of 23yr olds. That’s all. In fields like this, academics only know the basics. They’re needed, don’t get me wrong, in just the same way that nursery-school teachers are needed to teach children to count.
PhD is entry table-stakes to start work at companies like that. You make the coffee, and re-learn how it’s *actually* done by people with thirty uears more industrial experience than you.
Even in the USA, a full professor makes $150k. In a company like Cadence, if you’re even *competent* plodder you make $300k in five years. Somebody actually driving the innovation at mid-career is making double that, and more senior tech people well over a million.
Chip EDA software is some of the most clever and IP-intensive software on the planet. And by IP, I don’t mean “people know what it does, but you aren’t allowed to copy it”, this is classic “trade-secret: it’s just better than anything you have, how it does what it does is unknowable, but it just is”. This is not at all like software compilers.
They are in fact very rough around the edges. I've one really used commercial grade chip EDA at uni and compiler bugs were a perennial issue: they simply don't get the use and testing of software compilers. Indeed at times Cadence couldn't compile code generated by its own schematic capture tool. The code itself was generally fine, it was the compiler at fault.
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I assume their EDA offering is US based (an acquisition?) which makes it subject to this restrictive US trade trumpery.
Purely home grown (German or European) products presumable would fall outside these controls but I have previously underestimated the chutzpah of the reach of US extraterritoriality.
All they are doing is speeding up the process by which the Chinese blag, pinch, smuggle or reverse engineer stuff and then develop it faster than GAFA do, or find more effective alternatives. It may prompt them to roll out cluster-based systems or self-adapting chips. GAFA hasn't really innovated much over the last few decades (AI is a scam and doesn't count). It establishes a platform, freezes development and defends it with lawyers, buying out competition. It should be reasonably easy for China to outdevelop them, if forced to and funded by the state as a political imperative.
All these people have been saying for 10 years China would catch up within 2-3, you know, the last ¬10 years of the trade war with Trump and Biden. Yet here we are. Whilst China may have a massive middle-class I don't think even western companies would be able to make EDA tools if they had to start from scratch again, all that knowledge is long retired and acquired and commoditised. I also doubt the autocratic culture in China is going to bode well with technology and innovation. It is built within an exclusive ecosystem and decades of development with TSMC and other various foundries. It's hard to innovate with a gun pointed at your head or the threat of re-education for you and your family and virtually no credit given if you manage to succeed. When you promote only party loyalists you get the likes of Soviet era imcompetence. Thankfully they don't have any RBMK reactors.
What's more is the mass influx of Chinese students I saw in the 2010s in universities. They were all heroes of the new China state, here to poach our best academic knowledge and transfer it to China, always a ring-leader monitoring them all closely, ensuring they don't use social media or socialise outside their Chinese-national bubble. Well, everything is now under lock and key under the guise of cyber-security in semidonductor companies, and Chinese nationals aren't allowed near it. Try getting access to TSMC libraries today, and you need to be approved by hand and their data server if local has to be under surveillance constantly if you want TSMC to even consider to work with you.
One way China could leapfrog EDA is with AI. Currently EDA are reluctant to use AI in any real way (RTL to GDS) due to the possiblity they could kill their own golden goose that is the mass of renewable licences needed to run stuff.
Without the need to conserve this status quo there is the potential for investment & innovation.
Ha ha! This is total BS on the IP of EDA tools and the USA having ANY SAY on who or who does not have access to those tools! The next few days will be a DOOZY once we introduce our fully-ITAR-FREE (i.e. NO USA involvement in design and manufacturing for our in-house-built software OR hardware whatsoever!) 128-bits wide, 2 THz clock speed combined-CPU/GPU/DSP/Vector processor tape-out design for y'all to download, 3D-print and/or modify to your heart's delight ALL UNDER world-wide, fully-free and open source under multiple open source licences including but not limited to GPL-3 for the design, manufacturing processes, the final hardware and all software and documentation and help media!
The USA and Intel, AMD, IBM, ARM, Qualcomm, NVIDIA, Samsung, TMSC, Huawei, NEC, Sony, etc are ALL SCREWED with our design! And I should note that we have some of the WORLD'S ABSOLUTE BEST CHIP DESIGNERS and EDA developers here at work in Canada and NCA (North Canadian Aerospace)!
All Yours!
V
P.S. I designed and coded the real-time 2D-XY/3D-XYZ SOBEL and CANNY edge detection, pixel-to-vector conversion and Million+ objects per frame automated object recognition and tracking code and multiple RGBA/YCbCrA/HSLA/CMYKA and other pixel processing and line/curve/fill drawing routines for this super-processor chip!
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