AMD pumps Epyc core count to 192, clocks up to 5 GHz with Turin debut Intel's 128-core Granite Rapids Xeons are barely two weeks old and AMD has already fired back with a family of fifth-gen Epycs that boast double-digit IPC gains with up to 192 cores or clock speeds as high as 5 GHz. We got the details at the Advancing AI event in San Francisco on Thursday, and a close look at the House of Zen' …
Just love this AMD-Intel competition! In the 64C "HPC modeling and sim" comparison, it's nice to see Turin giving 33% uplift over Genoa/Bergamo. The 60% better perf than Platinum 8592+ makes one wonder at first, but the base/boost clocks on Turin 9575F are 3.3/5.0 GHz (in the article's table, at 400W) compared to 1.9/3.9 GHz for the 8592+ (350W). It should be interesting to see if Granite Rapids' MRDIMM, and/or AMX, can compensate for lower clockage, possibly with a 72C 6960P, with its 2.7/3.9 GHz, that can be stepped down to 48C at 3.1 GHz if needed (450W).
Looking forward also to AMD swapping Turin's I/O die memory controller (chiplet) for a MRDIMM version and even more oomph in this now reinvigorated competition!
Same reason Intel use real lakes as their names (they used to use bridges), or AMD currently uses stars for it's GPU (it used to use tropical islands).
Making up a name is too expensive legally as you need to check nobody has used it before, there are no trademarks, ect.
Using the name of a real place means you don't need to worry about any of that, so you can just pick a theme and run with it for a decade.
A job that ran 1 hour in 1970 (mainframe at 1MHz, 64MB main memory) can now run in < 1 second (and >256x larger in main memory). Maybe time to mine those old papers, given that some of those "impractical" brute-force algorithms might now be quite practical, especially if nothing better has come along?
OTOH core store access times didn't change with the access pattern but DRAM access times get substantially longer for anything other than locations in the same row.
IRL this only matters for people who need serious performance. The sort who rewrite their programs to access array rows instead of columns (or vice versa, depending on their language).
But if you're not that bothered about speed or capacity, why are you reading this article?
I think you're off by a few orders of magnitude. It is more like a job running in a week or a month taking a second on that Epyc. Also, no one had anything remotely close to 64 MB in 1970. The Cray-1 supercomputer that came six years later had only 8 MB. Even my phone has 1000x more RAM, and just one of its E cores could run rings around the Cray-1. Heck, my watch could run rings around it! That Epyc can hold 12 TB of RAM, which is 1,500,000x larger than Cray-1...
The delta between modern memory-system average read- and write-times is due, I believe, to cacheing.
I've not heard/read of a real-world computer which used core memory and cacheing.
(I'm not gonna write here about computers using delay-line memory, storage-tube memory, or drum memory. But there was a research computer developed in the 1960s which had an auxiliary associative memory...)
IBM 360/85 introduced in 1968 here
My figure for main memory of 64MB was high, the biggest of the 360's hit 4MB, 16x smaller, but the clock speed is around about right.
Note of course that these were mostly single processor machines, except the /65and /67were dual processors.
Keep in mind that while having umpteen cores at your disposal gives you theoretically vast processing power applying all that power to a single program (or single dataset) is very tricky.
Effectively you've got a server farm on a single board (or in this case single chip).
Core storage write times could vary if you were using indirect addressing in part of your program, vs direct or relative addressing. The indirection (depending on sub-mode) could require a memory read to fetch part of the effective address. Some old systems let you daisy-chain indirect addressing as much as you wanted.
I've had reasonable luck getting low-spec systems from bargainhardware.co.uk then swapping the CPUs out for bigger ex-cloud ones
(though I have an intermittent memory fault on a 104-thread / 288GB Skylake box which is going to be a bit of a bugger to diagnose, dual-Skylake means the memory modules come in sets of twelve and I'd rather have dinner at the Fat Duck twice than buy 12 new 32G modules at £42 each)
I want one with huge masses of memory ... for no reason other than I want one !!!
No idea what I would do with it ... please don't mention anything AI [cough spit] related !!!
Never let that stop you if you can afford it !!!
[Even if I blew my a chunk of my pension pot on a stoopid setup, it would be out of date in 6 months. :( ]
:)
Apparently very little - the Phoronix review https://www.phoronix.com/review/amd-epyc-9965-ampereone/5 says that the Turin chip idled at as low as 19 watts (whilst measuring it at 461 watts flat-out)
That's getting to the point where RAM power consumption and the rest of the platform are more significant than the processors, which is really all a processor designer can hope for.
And it indicates AMD are paying attention to this - Ampere's chip which was also examined in the Phoronix review never used as little as 100 watts
https://www.phoronix.com/review/intel-xeon-6980p-power/7 shows (dual-socket) Granite Rapids power consumption between 63 and 1085 watts
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