TSMC boss says one-trillion transistor GPU is possible by early 2030s

3D chiplets will be the key to building the world's first one-trillion transistor GPU, says TSMC chairman Mark Liu and chief scientist H.-S. Philip Wong. The semiconductor industry is always going to want to cram more transistors into processors, but as Liu and Wong outline in a IEEE Spectrum report, AI has made this demand …

[Pascal Monett]

So, Intel will be first

Of course it will. Until it isn't.

Intel hasn't been first since a while. I wish Gelsinger all the luck, but Intel's build performance has been lackluster for more than a few years now.

Wait and see.

[Yet Another Anonymous coward]

2.5D -> 3D

Ours will got to 3.5D

Buy 3 dimensions, get one half-off !

[A Non e-mouse]

Two minor questions:

1 - Power. How much power are these things going to draw? The current high-end GPUs are taking 1kW. Are we talking 10kW for these beasts?

2 - Cooling. If you're stacking chiplets, how are you going to cool the middle ones?

[Snowy]

Does it scale that way?

Intel 4004 used 0.5 watt for 2300 transistor scale that up to 1 Trillion and you get about 217,391,304W, I would hope for some efficiency gain but it is still going to use a lot of power

[MachDiamond]

3. How painful will QC be when there's 1 trillion plus points of failure in production on each chip

[jmch]

Not an expert, but smaller node allows lower power, so going down to 2nm will mean lower power per transistor. Ditto if they can come up with some cost-effective exotic material with lower resistance. But in any case, if they want 100X or 1000X the transistors, 10X the power is the least to be expected. For cooling, maybe they could have some liquid cooling going through gaps in the 3-D structure? Although at that point you're getting to scales where fluids behave very differently.

[David Hicklin]

> but smaller node allows lower power, so going down to 2nm

also no expert but I seem to remember reading that the node size ceased to have much effect on the transistor size some time back as you are starting to hit the minimum number of atoms per gate limit

[Ken Hagan]

If the lower chiplets are memory, they will be basically idle most of the time and could be designed to trade some capacity in exchange for a ridiculously low leakage current. The power per unit area might not be much higher than today.

[Lucy in the Sky (with Diamonds)]

Obligatory question

But would it be able to run Crysis?

[Inventor of the Marmite Laser]

Y'know, we've come one heck of a way since the OC70 transistor.

[Anonymous Coward]

NVDA is not the only game in town

Cerebras Systems has already surpassed this by leaps and bounds with Wafer Scale Engine 3 which has 4 trillion transistors and is the size of a dinner plate.

[Roland6]

Re: NVDA is not the only game in town

Relevant article here: https://en.wikipedia.org/wiki/Transistor_count

Probably explains why Intel are saying GPU.

[sammywhammy]

Re: NVDA is not the only game in town

The delineation is arbitrary, as these GPUs are not being used for graphics at all. The article specifically cited "needs" for growing AI demand and also talks about reticle limits. The real cost of AI is training where the constraints are memory, bandwidth, and power consumption - all of these "needs" are much better addressed by a solution such as what Cerebras offers.

[Anonymous Coward]

Re: NVDA is not the only game in town

They also blow that 800 square mm limit away. Their latest product is 46,225 square mm.

[Sparkus]

The IBM Telum chipset

in the current Z series of mainframes is designed and fab'd with all of these stacking and interconnect technologies in mind (and fab'd in 7nm)