back to article Nvidia rival Cerebras says it's revived Moore's Law with third-gen waferscale chips

Cerebras revealed its latest dinner-plate sized AI chip on Wednesday, which it claims offers twice the performance per watt of its predecessor, alongside a collaboration with Qualcomm aimed at accelerating machine learning inferencing. The chip, dubbed the WSE-3, is Cerebras' third-gen waferscale processor and measures in at a …

  1. I am David Jones Silver badge

    “Freedom units’ teehee

    1. LogicGate Silver badge

      I believe the term should be stormtrooper units...


      1. Yet Another Anonymous coward Silver badge

        We refer to them as "medieval" Allen keys

  2. Mage Silver badge

    Ivor Catt

    Ivor Catt developed and patented some ideas on Wafer Scale Integration (WSI) in 1972, and published his work in Wireless World in 1981, after his articles on the topic were rejected by academic journals.

    I remember those articles. Also later ones about autorouting to avoid defects.

    He's still alive.

    1. LogicGate Silver badge

      Re: Ivor Catt

      And that is the curse of being too far ahead. The Patents run off before the uptake takes place, leaving the inventor with no benefit.

      Now, had he come up with a mouse with big round ears, then he would be a rich man today. (yes, I know that steamboat willie just exited protection)

      1. This post has been deleted by its author

      2. Yet Another Anonymous coward Silver badge

        Re: Ivor Catt

        The clever bit isn't saying: you should use all the chips on this wafer in one computer rather than chopping them up and re-assembling them on a PCB - it's making it actually work.

        Otherwise I invented the intergalactic hyper death-ray battleship on my school book in infants

  3. Mike 137 Silver badge

    An unanswered question

    "The 4 trillion transistor part is fabbed on TSMC's 5nm process and is imprinted with 900,000 cores and 44GB of SRAM"

    That's an awful large target for production flaws. I wonder what the yield will be.

    1. Yet Another Anonymous coward Silver badge

      Re: An unanswered question

      |The engineering that makes this possible is mapping out and routing around the bad cores.

      The problem has always been that this costs money and wafer area, so it was always more cost effective to chop the wafer up, test each chip and sell them separately

      It's only with tasks that need a bazzillion cores and 44GB of ram for a single task that this thing starts to make sense

      1. RegW

        Re: An unanswered question

        Wot! Like a SCIS drive bad sector map?

        Well isn't life just one big circle!

  4. HuBo

    A yummy chip platter

    I quite like Cerebras' non-standard approach to computer architecture, going against the grain of "accepted" concepts, and into a successful dataflow perspective, with distributed memory, on a single wafer. Doubling performance at the same power level by going from the 7nm WSE-2 to the 5nm WSE-3 is very nice. Given that WSE-2 had 850,000 AI cores and WSE-3 has 900,000, should we presume that the higher performance results from faster clocks?

  5. Morten Bjoernsvik

    23KW per rack

    How do you cool this? Sounds terrible expensive.

POST COMMENT House rules

Not a member of The Register? Create a new account here.

  • Enter your comment

  • Add an icon

Anonymous cowards cannot choose their icon

Other stories you might like