MIPS snags top SiFive brains to amp up RISC-V business Chip designer MIPS has picked up two former senior staff from SiFive in a bid to boost its RISC-V development efforts. MIPS, the company that created the processor architecture of the same name, is now looking to the RISC-V open instruction set architecture for new products under the eVocore name. The eVocore P8700 has been …
Last I heard, more ARM chips ship per year than the entire population of the Earth. And I think RISC-V might be in that league, too.
The world’s third-most popular CPU architecture might still be MIPS. The last figure I had for that was something like 840 million chips per year. Of course, there would be hardly any money left in those chips nowadays, in terms of IP Ilcensing.
No way MIPS or RISCV are 2 and 3, there must be many basic microcontroller like cpus that do boring things like scan keyboards or control the fridge light that outsell them easily. Even a basic board with a MIPS or RISCV cpu woul dhave a few of these simple CPUs controlling boring stuff like keyboards, usb etc.
Arm and RISC-V have both been very rapidly replacing 8 bit MCUs in new products. They are just SO MUCH more convenient to program than a PIC or 8051, and there is now even no price advantage to 8 bit with both Arm and RISC-V being available in $0.10 MCUs with 2 or 3 KB of RAM and 16 KB flash.
Right, but 10 cents is just one particular market segment. It’s a loooong way from what I would describe as the low- cost end. There’s Padauk at 3 cents per, or 2 cents in Shenzhen in real volume. Neither ARM nor RISCV attempt to compete in that segment.
> there must be many basic microcontroller like cpus that do boring things like scan keyboards or control the fridge light that outsell them easily
"microcontroller" is not a chip architecture, it is a uage of a chip. Microcontrollers are usually based on existing cpu architectures, like 68000, MIPS, ARM, RISC-V. Therefore that microcontroller in the keyboard is probably a 68000 or ARM based microcontroller, etc. All the major architectures tend to have cut-down microcontroller designs, e.g. SSD controllers often have ARM-based chips in them, WD uses RISC-V microcontrollers on their HDDs (replacing ARM).
Thanx for the correction about usage of the term microcontroller, however the cpus you mention easily surpass the usage of RISCV and MIPS.
Of coure SSD controllrs have arm chips, an SSD is moving a lot of data, which means the CPU used must be running at speeds signfiicantly faster than a simple 16 bit 68k or 8 bit Z80 etc. Not all cpu usage is for such speed focused usage, i was referring to the signiicantly simpler devices like fridges, washing machines and more where a simple slow cpu like a 8 bit or even 16bit is more than enuff.
> i was referring to the signiicantly simpler devices like fridges, washing machines and more where a simple slow cpu like a 8 bit or even 16bit is more than enuff.
You mean like the Arm Coretex M0+?
The NXP LPC800 based on it has in its reference design portfolio examples such as:
And (using TI's page for their Coretex M0+ chips) they start at 18c e.a. (for 1000 unit quantities).
As I said, most microcontrollers for most common applications (fridges, remote controls, chargers, vacuums, etc.) are going to be based on commonly used architectures - microcontroller specific variations, but still variations on well known architectures - such as ARM, Motorola (M68000), and what have you.
> And I think RISC-V might be in that league, too.
Maybe not quite, but soon.
In December 2022 at the RISC-V summit we were told more than 10 billion chips with RISC-V in them. I don't know if that was updated this year, but Qualcomm said they shipped a billion chips with RISC-V in them in 2023. Back in 2017 Western Digital announced they would soon be shipping over a billion RISC-V chips a year. I haven't seen updates on that. In December 2019 Samsung said the Galaxy S20 would have RISC-V cores controlling the 5G radio and the camera. Assuming that has continued and spread through the range that's quite a few cores too. Samsung certainly continues to be interested in RISC-V. They are porting DotNET and their Tizen operating system to RISC-V for use (according to job adverts) in future TVs and other products.
A few months ago I read a concise and excellent book called "The RISC-V Reader: An Open Architecture Atlas". About half the book's contents discuss the RISC-V instruction set and provide examples of use, while the other half is of the form "Previous generations of CPU architectures did [such-and-such] which history has shown to be useful so RISC-V embodies those ideas, but previous generations of CPU architectures also did [something else] which history has shown to not be useful, so RISC-V avoids those mistakes." For better or worse, the two different kinds of contents are inter-mingled in each chapter of the book (I found that inter-mingling to be useful, but not everyone will). The main takeaway I got from the book is that the RISC-V architecture is as elegant as it is because its designers "stood on the shoulders of giants before them to see farther". That, combined with RISC-V being a much newer architecture than x86 or ARM means that RISC-V contains several orders of magnitude fewer instructions than those other CPU architectures.
Of course, a product being elegant is rarely enough to help it compete against the incumbent market leaders. But a few other characteristics of RISC-V do help in that regard.
First, the RISC-V specification is open-source, so this helps to drive down costs, which matters to a company that makes, say, a USB/Bluetooth keyboard that needs a tiny embedded CPU and sells in a market with competing keyboards priced from as little as £5.00.
Second, the RISC-V specification contains just 47 required instructions, and all other instructions are optional but packaged into logical groups (e.g., integer multiplication and division, floating point instructions, bit manipulation instructions, vector instructions and so on). It is possible to implement a 32-bit RISC-V CPU for the minimal required instruction set in just a few tens of thousands of transistors, and this can increase yield rates from silicon wafers, thus resulting in a very low manufacturing cost, while still giving developers of embedded systems a modern, clean 32-bit instruction set to work with. At the other extreme, it is expected that a 64-bit RISC-V CPU with all the optional instructions, lots of CPU-internal parallelism (out-of-order execution, superscaler and other buzz words), and tons of on-board cache could be implemented with many billions of transistors so it can compete against powerful ARM/x86 CPUs in server machines.
Third, because the RISC-V architecture is new, lean and does not carry the same backwards-compatible baggage as ARM/x86, it looks like a RISC-V CPU might use less electrical power as an ARM/x86 CPU that provides similar performance. This electrical power efficiency will help RISC-V not just in the embedded systems market, but also in the data centre and supercomputer markets, where managing heat build up is a big concern.
My interest in RISC-V is that I want to buy a development board so I can ensure some (to be) open-source software I am writing will work well on RISC-V. From what I have seen, it looks like RISC-V manufacturers are taking a bottom-up approach to the CPU marketplace. They are initially attacking the low-cost embedded systems market, and are slowly moving up towards more powerful CPUs. The last time I checked (a few months ago), the most powerful RISC-V CPUs were 4-core devices that were approximately as powerful as a Raspberry Pi 4, but one manufacturer was setting a motherboard with with many such CPUs to provide a total of (if I remember correctly) 64 cores. A year earlier, the most powerful RISC-V CPU I saw was only half as powerful as a Raspberry Pi 4, so doubling performance in just 1 year shows progress is being made. I assume it will take a few years before we start seeing desktop-grade RISC-V CPUs, but already having some companies developing multi-socket motherboards suggests there won't be a significant delay between desktop- and server-grade RISC-V.
Yes, it does look like a lot of care has gone into the design of RISC-V. Also did you notice the approach they took to vector ops? Instead of the fashion for SIMD (and the consequent combinatorial explosion in additional instructions that makes a mockery of the term “RISC”) that has infected about every other major CPU architecture still in use, they went back to how good old supercomputer genius Seymour Cray used to do it, with long-vector pipelined operations, and revived his approach.
Im not sure exactly about your criticism of SIMD, but i would have to agree that having the size or width embedded in the cpu instruction means each time they add more registers the previous instructions become outdated and they have to allocate new unique op code for the wider registers.
The ARM v8 (64-bit) ISA is only 13 years old, according to Wikipedia and was a significant cleanup of the previous ARM v7 and previous (32-bit).
So although RISC-V is modern and elegant, ARM v8 is not as old as you think.
https://en.wikipedia.org/wiki/ARM_architecture_family
Isnt optional packages make for fragmentation.
Look at Apple, it was nt that long ago their Macs were both 32 and 64b and then they dropped 32bit.
Writing binaries to support optional cpu packages makes for a complicated bulky mess where the runtime has to test cpu features and then and include all combinations.
It's impossible to know how many RISC-V processors have been deployed, since anyone with the necessary resources can produce the silicon : companies only have to be members of RISC-V International if they wish to advertise that they're using the ISA. I maintain that the estimated figures are conservative, based on the activity of the major RISC-V players. It's entirely possible that there have been unmarked, 'simple' microcontrollers in devices for as long as a decade now.
This makes perfect sense IMHO. MIPS Tech. was founded by John L. Hennessy (of Stanford and Alphabet, not Cognac) in 1984, who is a long time collaborator of David A. Patterson (Berkeley, RISC-I,II,III,IV,V). They won the 2017 Turing Award together for their work on RISC and co-published many works (eg. Computer Architecture: A Quantitative Approach).
At its essence, RISC-V can be thought of as the (d)evolution of MIPS (after all the good bits were removed). If MIPS Tech. had followed a straight line in its company progression (rather than multiple takeovers and bankruptcies), it would have most likely ended-up making RISC-V chips a couple years ago, as it is gearing to do now (since at least March 2021). Snagging top SiFive brains to help with this is the right move to make indeed!
Eh-he! Well, the architecturally visible delay slots in MIPS did help its performance, without a need for extra Out-of-Order (OoO) execution machinery (front and back ends). As stated in Section 2.5 (Control Transfer Instructions) of The RISC-V Instruction Set Manual, Volume I: Unprivileged ISA, Document Version 20191213:
"Control transfer instructions in RV32I do not have architecturally visible delay slots".
Consequently, in RISC-V, the corresponding performance enhancements have to rely on extra hardware (eg. OoO). But I'll admit that RISC-V's variable length instructions (esp. 16-bit compressed) can be useful to increase IPC if the HW implementation includes two or more ALUs among its execution ports. Apart from that, RISC-V remains not-an-evolution from RISC-III and RISC-IV (even RISC-II) -- we'll need RISC-VI for that IMHO.
Delayed branches were considered a “good thing” for only a brief time in the history of RISC. That time lasted long enough to inflict legacy baggage on both SPARC and MIPS (that I can recall) that they had to carry around ever afterwards. By the time of IBM POWER, by 1989 or so, it was thankfully no longer considered necessary. In fact, IBM claimed that, with all the hardware parallelism going on, branches could frequently take zero effective clock cycles during execution.
These are great points (IMHO). The POWER architecture has indeed evolved substantially from its "humble" beginnings to POWER9, POWER10, and the upcoming POWER11 (2025), with chips in enterprise, datacenters, HPC machines, and (at some time) PCs too. I don't see RISC-V has having evolved this way from RISC-II, RISC-III, and RISC-IV. In fact, in Section 28.1 “Why Develop a new ISA?” (in The RISC-V Instruction Set Manual, linked earlier), the authors compare RISC-V to OpenRISC only, and OpenRISC is pretty-much a no-frills RISC.
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