back to article Google formally gets to work on Android on RISC-V

Google has significantly advanced its efforts to have Android run on CPUs that use the RISC-V instruction set architecture. A Monday post to the ads and search giant’s open-source blog opened with an explanation that Android “supports many different device types and CPU architectures” then added “We’re excited to be adding a …

  1. Mockup1974 Bronze badge

    rambling a bit

    >RISC-V is permissibly licensed, meaning chip designers are free to use the architecture but aren’t compelled to share their work as is required under other forms of open-source license.

    And exactly this will be a problem. Many incompatible ISA extensions, chip designers adding proprietary stuff that only their special snowflake chip will use, no standardized firmware or bootloader - despite being open source, the implementation will just end up just as closed as ARM or even worse. I guess x86 remains king for us FOSS nerds, because one OS build can run on all x86 devices.

    For smartphones, the only manufacturers that allow unlocking the bootloader and installing other Android distros are Google (Pixel) and some niche vendors like Fairphone. (I'm not even sure about non-Android stuff like mobile GNU/Linux distros, can they run on bare metal or do they need a thin layer of Android at the bottom?) A big problem also is that every ROM needs to have a specific image for each device. So even if you have a device with an unlockable bootloader it may not have any ROMs available because someone needs to develop it specifically for that one device. And don't get me started on the fact that the Linux kernel never gets any updates in Android smartphones, which I think is because of all the proprietary drivers patched into the OEM kernel and not supported by the mainline kernel.

    Is RISC-V really going to be different just because the ISA itself is open and royalty-free?

    On the desktop we have POWER for that by the way, which is also open and royalty-free. But as far as I know there's only one vendor of desktop hardware, namely Raptor Computing.

    1. UK DM

      Re: rambling a bit (yes you are :)

      So far this ISA extension hell you speak of has not occured. This situation already exists for intel/AMD over MMX though to AVX. Solutions exist in that space already to manage software. I see little difference in the specification and bickering with choping and changing of available extensions between intel/AMD than the vision of a potential future with RiscV you are so fearful of.

      I can see RiscV on budget phones working well, budget because they under perform on user expectations, not budget just because they are RiscV.

      What really is not clear, is if RiscV as an architecture can get anywhere near ARM on the metrics what count in ARMs highend market segment. It may become apparent within the next 5 years that the high performance general computing goal isn't within architectural reach.

      However it looks to eat the ARM low end segment for breakfast as things stand, so maybe performance mobile computing and performance cloud computing is relatively safe. Maybe ARM in cloud will face competition, since while ARM provides cost efficiency, there is plenty of cloud use that could use even better cost efficiency RiscV can bring (again this comes from other factors like performance per watt, datacentre density, not because it is free and open-source).

      Being open-source will only financialy benefit those that can extract value from that aspect of the proposition and is not expected to significantly improve end user cost of ownership. The first movers are pocketing the gains from their risk. (Yes that was a pun)

      1. JessicaRabbit

        Re: rambling a bit (yes you are :)

        RISC-V is just an ISA. The performance of RISC-V chips will mostly come down to how the internals of each chip is implemented and that is up to the chip designers. The ISA just describes the instruction set, registers etc. To quote Wikipedia:

        "An ISA specifies the behavior of machine code running on implementations of that ISA in a fashion that does not depend on the characteristics of that implementation, providing binary compatibility between implementations. This enables multiple implementations of an ISA that differ in characteristics such as performance, physical size, and monetary cost (among other things), but that are capable of running the same machine code, so that a lower-performance, lower-cost machine can be replaced with a higher-cost, higher-performance machine without having to replace software."

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