AMD's latest FPGA promises super low latency AI for Flash Boy traders

AMD has refreshed its Alveo field-programmable gate arrays (FPGAs), promising a sevenfold improvement in operating latency and the ability to run more complex machine learning algorithms on the customisable silicon. FPGAs are often used by high-frequency traders, an industry in which a delay of a few fractions of a second can …

[Bebu]

What could possibly go wrong?

High speed trades, derivatives, AI/ML which has exactly 0.0 insight in adversary with same - going to Hell in handbasket but now with a supersonic ramjet attached.

[A Non e-mouse]

However, using machine learning to guide stock purchases isn't always a sure bet

I thought the best method for wining on the stock market was just to purchae into a tracker fund that invested in the top 100 stocks.

[fpx]

The commenters above appear to misunderstand the nature of these trades. It's about detecting minuscule price differences between trades. I.e., if you see an offer for stock of company A at $10.01, and a purchase order for the same stock at $10.05, these traders will step in and buy the stock from the first trade and sell them to the second trade.It's a guaranteed profit, you just have to be a few microseconds faster than the competition. This guaranteed profit is sucked from the other market participants, since of course the fair thing would have been to let the two trades settle directly at $10.03.

[katrinab]

And the difference in price is usually far smaller than 4 cents. But do it with large amounts of money, millions of times per second, and it adds up.

[Nate Amsden]

what are those ports?

looked them up myself

"The Alveo UL3524 card hosts four 8-lane small form-factor pluggable (QSFP-DD) connectors that are housed within a ganged 1x4 QSFP-DD cage assembly with heatsink. It can be populated with QSFP or QSFP-DD direct attach copper or optical modules supporting up to 7W. The QSFP-DD can connect interfaces up to 100G using optical modules or cables. A 161.1328125 MHz clock is provided to the QSFP-DD interface such that different Ethernet IP cores can be enabled."

https://docs.xilinx.com/r/en-US/ds1009-ul3524/Network-Interfaces