back to article Intel starts mass production on Intel 4 node using EUV in Irish fab

Intel is preparing to kickstart high-volume manufacturing at its plant in Leixlip, Ireland with the Intel 4 process, its first production node using extreme ultraviolet (EUV) lithography. The Santa Clara chip biz is holding an event on Friday with CEO Pat Gelsinger and others such as Keyvan Esfarjani, chief global operations …

  1. Peter2 Silver badge

    Intel starts mass production of their Intel 4 node, which should let them produce chippery on a par or better than what AMD has been producing with the TSMC 5nm process, which is great news for Intel.

    The trouble is that TSMC deployed a 3NM node at the end of last year which apparently Apple bought the entire production of, and they started volume production on their 3NM E(nhanced) 3 months ago so AMD are probably already ready to leapfrog Intel's latest and greatest processors with something a generation ahead of them as soon as they are released.

    1. katrinab Silver badge

      Intel 4 is 7nm I think? Which means they are playing catchup with SMIC, and way behind Samsung and TSMC.

      Probably their 7nm will be better than SMIC's.

      1. Kristian Walsh Silver badge

        Nanometres are nothing more than marketing-speak these days. Transistor density is a better metric, but even that has caveats when you look at actual parts.

        “Intel 4” used to be called “7 nm”, but it offers densities better than TSMC’s N5: basically in the range 150~180 million transistors per square mm. First application for Intel 4 will be a CPU, which means the actual density will be at the low end of the process’s density range (density is the inverse of performance; SoCs have higher overall densities than CPUs because of all the DRAM; the transistor density of the CPU cores is lower to allow better heat dissipation during faster switching).

        Intel was traditionally more conservative about feature-size - it typically quoted the sparsest configuration, which is the one that gives the highest performance, while TSMC typically quoted the densest configuration, which comes at a performance penalty. Again, this makes sense when you consider that TSMC makes mainly system-on-chip dies on its smallest node, while Intel tended to use its smallest nodes solely for microprocessors. In the days when the audience was engineers, who understood this distinction, there was no problem, but in today’s media landscape with tech bloggers and marketing droids who just want a Holy Number to fixate on, it was making Intel’s shortcomings look bigger than they were.

        That’s not to say Intel isn’t behind. They are, but the next two years look interesting, because Intel 4 was the big step-change into EUV, and the pipeline that follows it is very rapid, much faster than TSMC’s. The next node down, Intel 3, is to start volume production mid-2024, jumping ahead of TSMC’s current N3 node, and only a year after the TSMC process (compare with Intel 4, which was three years behind TSMC’s N5). After that, it is Intel that looks like being first to crack “2 nm” (or “20 ångstrom” if you’re Intel...) in volume production, and it could be more than a year ahead of TSMC’s equivalent node. That will probably mean that TSMC’s N2 will be denser than Intel 20A when it arrives, though, because it’s generally true in fabrication that whoever has the newest process has the smallest node.

        1. Yet Another Anonymous coward Silver badge

          How does this work for ASML?

          Do they make the next generation machine for Intel only, and then the gen after that for TSMC only - so they switch who has the latest "nm" lead?

          Or do they make the same fundamental machine for both and then Intel / TSMC decide how far they push the envelope on it ?

          1. tuchie

            It is the same Lithography Tools that are sold to all Customers, but they only enables a minimum design-rule, governed by defraction limits. However that doesn't mean you have a complete manufacturing process that is capable of supporting that design-rule and doing so with sufficient yield to make it financially viable.

        2. Anonymous Coward
          Anonymous Coward

          To come out later do not equal to higher density.

          Intel 20A/18A does have backside power delivery, according to earilier Intel slides, PowerVIA will bring 10% reduction in size in Intel 4, so we can safely assume the same in Intel 20A/18A. I had reasons to believe that Intel 20A will be 5% density with 10% performance over TSMC N2, if what is currently published is the truth, intel 20A/18A will still bring around 2% in density and 7% in performance (educated guess only) over TSMC N2P which is their first generation backside power delivery, Intel's PowerVIA is a nTSV design i.e., the 2nd generation of backside power delivery from TSMC which is not on their roadmap (there will still be power line in M0 then run the copper to the other side so it did not route through M1, but intel is directly powering the M0 from the back, i.e. there is still area that Intel will saved over TSMC backside power delivery and the power is more direct by the Intel approach.

          Do you see the overheat, if you said this is purely Apple design flaw, that is just too navie, TSMC N3B is part of the problem, as I posted in another forum, TSMC N3B is a failure, no one will use it even iPhone 16 will drop it. Then you needed to talk about Intel Meteor Lake on Intel 4 / sierra forest Intel 3 vs iPhone 16 pro max, because if you look at this why no one except apple will use TSMC N3B, Amazon/bitcoin mining/specialised AI is a very good candidate for such a node, no, only Apple. In engineering point of view you can compare to Airbus A380, yes you build the largest airplane, but you use 4 engines and orders are going to 777 not to A380, same yes might be (just might be) TSMC N3B is going to be smaller than Intel 4 but at what cost (performance and density), it will only goes 1 node and the momentum is lost as anyway future N2 node will be on ASML High NA, the lesson learned in double patterning EUV is totally gone, the future required double patterning but on EUV High NA.

          Intel is already ahead of TSMC sorry but this is the truth, you needed to compare Intel 4 to TSMC N3E (which bring close to 0 scaling (in SRAM) to TSMC N5). Because Intel is now saying meteor lake will bring the 10%-20% power saving on the same performance over raptor lake, taking into account chiplet / tiles penalty, sorry to dash the fanboy of TSMC, this is the truth TSMC is no longer producing the highest performance transistor in the world is mass volume, Intel is now the king of transistor again in 2023.

          1. katrinab Silver badge

            But then again, my iPhone 15 Pro Max has single-thread performance that is basically the same, or maybe very slightly slower than intel's 13900K.

            This is comparing a phone running on battery power with passive cooling that charges from a 20W power source, with a flagship gaming desktop that requires 125W just for the CPU.

            1. Kristian Walsh Silver badge

              If you actually cared about performance, you would have bought the cheaper iPhone 15 Pro - it’s faster than the one you got. It appears that the Max may be thermally throttled versus its smaller sibling.

              There seems to be due to a thermal problem in general with the A17 Pro phones, and I think the blame for that is in Cupertino, not Taiwan. Apple may be trying to squeeze too much onto the chip. The rule about density versus performance holds true at every feature size, and the A17 Pro is a very dense design, even at a “3 nm” process. The root cause seems to be the desire to squeeze in

              more GPU cores, given that users are reporting the device getting extremely hot whenever it does anything graphics-intensive.

              1. katrinab Silver badge

                I care more about the screen size. My decision was between the 15+ and 15 Pro Max.

              2. tuchie

                I am old enough to remember when Apple were using SAMSUNG to fab their iPhone chips and SAMSUNG was reserving their leading edge capacity for their own Android chips.

                Back then Apple Fans would regularly claim that the older design-rules were more reliable, superior, etc.

                Where did those Apple Fans go?

      2. kat_bg

        Playing catch-up with SMIC??? Are you joking?

  2. Arthur Kater :-D ☺

    "So, yes, TSMC may have used EUV on an earlier generation tech than Intel but [that] doesn't necessarily mean Intel is behind in its ability to deliver a given node."

    Reality is Intel is far behind TSMC in it's ability to deliver 3nm products. TSMC has vastly more experience.

  3. Pascal Monett Silver badge

    "arguably the most complicated piece of machinery humans have ever built"

    100,000 parts, oooh.

    3,000 cables, aaaah !

    40,000 bolts and more than a mile of hosing - OMG !!!

    Sorry, Intel, have you checked out ITER ?

    The 23000-tonne ITER Tokamak is a complex assembly of one million components and an estimated ten million individual parts. Surrounding the central reaction ...

    You are so outclassed it's not even funny.

    1. Yet Another Anonymous coward Silver badge

      Re: "arguably the most complicated piece of machinery humans have ever built"

      But you can't order an ITER off the shelf

      1. katrinab Silver badge

        Re: "arguably the most complicated piece of machinery humans have ever built"

        Don't think you can order an EUV machine off the shelf either. Yes, I know Wish dot com claims to have one for £104.20 with free shipping, and Amazon claims to have one for £39.99, but I doubt either of them will actually work.

  4. squigbobble

    5 in 4

    I suspect that Intel is going to deliver 5 nodes badly in 4 years as they strive for supremacy in the Holy Number, as another commenter put it. Are they going to keep all the nodes in production or will some of them get dropped before they've even hit the plateau of the yield curve?

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