Will they be cooking bacon on the heatsink?
While they play Six Degrees of Kevin Bacon that is. Frankly, I'm a little disappointed that El Reg didn't ask these important... ahem... burning questions!
Intel has used this week’s Hot Chips conference in California to show off a 528-thread processor with 1TB/s silicon photonics interconnects that's designed to chew the largest analytics workloads, while sipping power. For those hoping for a hyper-parallelized Xeon, this isn't that. The chip isn't even x86 based. Instead, it …
> According to Intel, a 16-sled configuration would handle 8TB of memory, 2,048 cores, 135,168 threads
And presumably not some "simple" SIMD threads but genuine, full-fat, each going at it alone threads (that is, although probably many running the same code, not in absolute lockstep with each other).
That is an impressive number of threads. Therefore, to prevent a total meltdown into geek inadequacy:
> "If people want to give us money, we are more than welcome to build these things out."
Welcome? Did he not mean to say that "we are more than happy to build these things"? Although he could just be reporting that TSMC said they would be welcome back to have another run with this design.
Shame about the problems with the fibre connects - guessing at that scale you don't get much flex out of them. The mechanical requirements for making devices like this are boggling! Ignore the jibe about English, this is all just - wow!
Although it was on separate silicon, IBM had used on-silicon photonics in HPC systems some years ago.
The (failed) IBM Blue Waters PERCS system architecture, which was actually successfully rolled out to a number of organisations such as the European Centre for Medium-range Weather Forecasting (ECMWF), UK Met Office, Environment Canada and a small number of other companies and organisations (as well as a number of US government agencies) as the Power7 775 system, put a communication hub chip called Torrent onto the Power processor bus as a peer co-processor. This provided additional processing units to help with Data Reduction for RDMA, and a significant number of optical links (IIRC it was 32 multi lane links per Torrent chip, along with 32 copper links to other torrent chips in the same drawer), which were used to create a low-latency very high bandwidth mesh network which again if I remember correctly had a bandwidth of 16Tb/s (It was prominently labelled as the Terra-bit network on the optical backplane that linked the nodes into Supernnodes).
The drivers were added to AIX, and you can still see evidence of it in the HFI network types, although with the Power processor dropping the Power processor bus at Power8 in preference to PCIe direct on the processor, I don't think we'll see the same technology from IBM used again.
It's not quite the same scale as this Intel silicon, but you have to remember that this was designed over a decade ago!
I feel old for saying this, but I remember seeing some big headline on a PC rag once upon a time saying how you may never see the busy cursor again with Intel's new 133MHz Pentium chip. Of course at the time, DEC had been selling Alpha chips running at around 500MHz for some time. Virtually anything Intel and AMD do in the x86 space has already been done for like a decade-plus in other areas. ARM had its big.LITTLE design long before Intel came up with P and E cores, and it wouldn't surprise me at all to find out that someone else came up with the concept of multi-core CPUs long before AMD started selling the first dual-core x86 CPUs.
The System 360/67 was available in single- and dual processor ("duplex") versions. It was announced in 1965, with Michigan Terminal System (MTS) supporting virtual memory and dual processing available in 1968.
I remember using MTS in the mid-1970s. It was something of a mystery to us students how one machine could support so many 3720s (and other terminals) all at the same time. Amazing stuff for it's day.
It's actually not due to areas being switched off but rather because we have 8 core complex's composed of 6 cores with 2 cores being single threaded and the other 4 cores being 16 threaded so we get 66 threads per core complex. So we end up with 8×(2+4×16) = 528 threads, or 16 threads on 16 ST cores and 512 threads on 32 MT (16 thread) cores.
“That US military initiative seeks to develop a graph analytics processor capable of churning through streaming data 100 times faster than conventional compute architectures”
This initiative screams “surveillance” from all perspectives, but as long as it is our friendly US govt rather China it’s all hunky dory.