Intel promises to reduce droop with backside power in 2024

If you thought that backside power was something to do with eating too many cruciferous vegetables, think again: Intel is implementing this in future chips as a way of separating the power lines to transistors from the signal lines, simplifying chip layouts. Officially known as PowerVia, this technology is set to debut on …

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Presumably...

...the lower voltage loss in the phat wires will reduce their heat output as well. I wonder how much experimentation it took to decide whether the power or signal side should be deposited first.

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Re: Presumably...

The signal side has always been fabricated first, and still will with backside power. They fabricate the transistors as normal, then polish off the backside of the wafer to where the bottom of the transistor/signal layer is located, then build up the power delivery on the other (i.e. "back") side.

The thing I wonder about is the increased difficulty of handling/dicing those thinned wafers versus currently. I'm assuming the experience the industry has got from thinning DRAM and NAND dies to enable stacking provided the technology necessary to make this possible, and while Intel hasn't been doing that in their own fabs the companies making wafer handling equipment have already implemented it and Intel is able to leverage it. I'm not sure how the thinnness of those DRAM dies compares with how thin these dies will be.