back to article Chinese web giant Baidu backs RISC-V for the datacenter

Chinese RISC-V upstart StarFive has revealed that Chinese web giant Baidu has become an investor, to advance use of the open source processor design in the datacenter. On Chinese social media service QQ, StarFive wrote that it would "work with Baidu to promote the implementation of different forms of high-performance RISC-V …

  1. thames

    I suspect that Baidu have a list of things they are interested in using RISC-V for, but are not making solid commitments to any in particular on any specific time line until they've done some researching and testing.

    Overall though, I expect them to shift to RISC-V over a period of years. Anything else is too much of a risk given the current international environment.

    We can probably expect to see India going down the same road for the same reasons, just a few years behind though.

  2. Bartholomew
    Meh

    JH8100 ?

    From what I've read the first Dubhe based chip should be announced sometime in Q2 as the Fang Jinghong 8100 SoC (JH8100), probably 6 core (but might be 8) so at least four Tianshu large cores (normal frequency 2 GHz) and at least two Tianshu small cores (normal frequency 1.5 GHz); RV64GCBNVH; 12-stage pipeline design and can realise superscalar and deep out-of-order execution; hardware H.264 / H.265 / VP9 / AV1 codec decoding; estimated SPECint2006 9.0 / GHz, Dhrystone 6.6 DMIPS / MHz, CoreMark7.6 / MHz; support for 4K 60fps displays; a bigger GPU from Imagination Technology than the one used in the JH7110; USB3.0/2.0 (x4), full-featured Type-C supporting DP, PD and USB 3.2 Gen 2; PCIe 3.0 x8; built-in NPU (2 TOPS - Trillion Operations per Second) for artificial intelligence, which supports mainstream architectures such as TensorFlow; hardware security engines for AES / DES / HASH / PKA and China national secret algorithm; 4-channel digital MIC. CPU cluster computing cache coherence, via a built-in multi-core bus technology self-developed by Saifang Technology - Starlink 1.0. Starlink 1.0 has the characteristics of high scalability, low power consumption, low latency, and easy debugging. (delay can reach 13.5 ns, power consumption is only 0.27 watts).

    The plan was for the JH8100 to be manufactured with a 12nm process (For comparison, VisionFive 2 uses a JH7110 and the RPi4B uses BCM2711, both of which were manufactured with a TSMC 28 nm process), the real question is can that happen SMIC (with sanctions, removing TSMC as an option). Maybe that will delay the exact specification being officially announced.

    As well as keeping an eye on the JH8100 I'm also looking at the SiFive Horse Creek, which has no vector support (built by Intel Foundry Services on the Intel 4 process, aka 7nm process node):

    SiFive P500 (RV64GBC) quad-core processor @ up to 2.2 GHz; 13-stage, 3-issue high-performance out-of-order pipeline; Each core has 32KB instruction + 32KB data L1 private cache and 256KB L2 cache ; Up to 4MB L3 cache in a quad-core cluster; SPECint 2006 score of 8.65/GHz; DDR5-5600 memory controller interface from Cadence; Intel PCIe 5.0 PHY with x8 lanes; Synopsys PCIe Root Hub Controller; I3C, Quad and Octal SPI, UART, peripheral DMA ; 19 x 19 standard FBGA Package ; Supports Ubuntu 20.04 with Linux 5.17.4.

    The deal breakers for me would be if StarFive used a draft version instead of the ratified standard RISC-V extension, and if Intel tries to shove in a Intel ME chip (I do not want a chip in my CPU that can only run unauditable, encrypted and signed code updated by the vendor for a couple of years).

    But the SiFive/Intel board should land sometime this year, the JH8100 SoC once announced will probably take another six months to a year and a half until it is on a board that can be bought.

    1. An_Old_Dog Silver badge

      Flies in the Ointment

      That's mostly-great, buuuut:

      (1) "and deep out-of-order execution" implies vulnerability to Spectre and/or Meltdown attacks. See: "A cross-process Spectre attack via cache on RISC-V processor with trusted execution environment" (https://www.sciencedirect.com/science/article/pii/S0045790622007613#aep-article-footnote-id1), and,

      (2) "and China national secret algorithm": like the non-Chinese world is going to trust that -- and will not wonder if there may be backdoor instructions included as well.

      You're right about the draft version vs ratified version, and about the IME.

      1. Bartholomew

        Re: Flies in the Ointment

        > national secret algorithm": like the non-Chinese world is going to trust that

        With nearly 18.47% of the earths population, I see no harm in China hardware selling with their own encryption standard, there is a big enough internal market. Why would China ship with only "trusted" encryption standards. Dual Elliptic Curve Deterministic Random Bit Generation comes to mind, where the NSA (Bullrun decryption program) influenced NIST into fully endorsing the weakened backdoor. And RSA set it as their default.

        There is public source code for all the "national secret algorithm"'s on <a href="https://github.com/guanzhi/GmSSL>github</a>.

        SM2/SM3/SM4/

        SM3 (hash) https://en.wikipedia.org/wiki/SM3_(hash_function)?useskin=vector

        SM4 (cipher) https://en.wikipedia.org/wiki/SM4_(cipher)?useskin=vector

        SM9 ...

  3. IGnatius T Foobar !

    Take your pick...

    Take your pick ... a chip that is bugged by the Chinese government, or a chip that is bugged by the Chinese *and* US governments?

  4. Ken G Silver badge

    Upstart?

    When does a startup become an upstart and does it only happen if they're from China?

POST COMMENT House rules

Not a member of The Register? Create a new account here.

  • Enter your comment

  • Add an icon

Anonymous cowards cannot choose their icon

Other stories you might like