After less than half a year, Intel quietly kills RISC-V dev environment Intel has shut down its RISC-V Pathfinder – an initiative it launched less than six months ago to encourage use of RISC-V CPU designs. Pathfinder was launched in August 2022. A joint press release from the 30th of that month includes a canned quote from Vijay Krishnan, general manager for RISC-V Ventures at Intel Corporation, …
Interesting that the price of microcontroller-type processor chips seems more dependent on the number of legs available than the actual functionality - I wonder whether the lower pin variants (with fewer IO ports, fewer peripherals etc) are actually the same parts through the whole range?
Absolutely not. A reasonably close parallel in the ARM ecosystem is that the Cortex-M0 used as a programmable engine in a lot of low-end microcontrollers (and some higher end devices like PCIe switches) is not very closely related (on silicon) to the ARMv8.2 CPUs used in the data center products (and the Pi 4).
All the CPU "type" tells you is that it runs a particular instruction set, much like the original "P5" Pentium of 30 years ago runs the same base instructions as the latest 13th-generation Core i9! So being a RISC-V CPU doesn't tell you much about the capabilities of the processor, just how software written for it is compiled. Details like memory accessing, optional extensions (like float point or vector operations) bus architectures and so on can, and indeed will, be very very different.
So the low-leg-count RISC-V processors that you can (apparently) buy for $0.10 are only faintly related to things like the SiFive P670 engine. But code compiled for the former will run on the latter (although it probably won't do anything very useful, as the former will have totally different embedded peripherals than the latter, which will do I/O by talking PCI Express, etc...)
I was actually thinking of theSTM ARM Cortex-M0+ parts - STM32L07x for example - where any given part is available[1] in pin counts from 32 up to 144, and where code written for the smaller part runs unchanged on the larger and vice versa provided none of the extra pins are used. That is, parts with the same generic part but different packages; certainly not between families and almost certainly not between closely related families with different peripherals.
Though it is handy to be able to use an L071 in place of an L073 if you don't need the touch interface, for example.
[1] for some value of 'available', these days!
A very simple reason for that. Think of a square of silicon. Each contact pad per pin at the edge is about 150 micron apart, because that’s the minimum for a flip chip. Make a 32-pin chip, that’s 4mm perimeter = 1mm square. Now drop a microntroller CPU into that, 60kgate, even @45 nm = 0.03mm2. The CPU itself nowadays is a small dibble in the middle of an ocean of wasted silicon area. The CPU area itself is totally irrelevant. By features, you probably mean small IP blocks of one type or another; most of these will be sub 10kgate, hence they come “free”. On-chip RAM is not so irrelevant. Just 32kB is 20x the area of the CPU execution units….and there’s your 1mm2, and also the reason why your microcontroller probably has 32kB of onboard RAM.
The RISCV angle is that the RISCV folks have deluded themselves that anyone wants “pared down” CPUs of 10kgate area. As you can see above, customers simply don’t care, because the silicon area is determined by pin count and not by CPU area. They *do* care about power consumption, but power consumption is mostly determined by: RAM access (which ISA doesn’t actually make much difference to, long story) and 30 years worth of tips and tricks in smart clock-gating and power-domain gating, which are all proprietary.
Low price chip sets reduce the number of pins by communicating via serial rather than parallel bus protocols. You don't need 128-bit data busses for cheap systems. That's why these microcontrollers all have 8 pins. The rest of the post makes no sense if unless you are building something that is not a microcontroller... I guess the clue is that these 10 cent microcontrollers exist in the real world while you are saying they shouldn't?
Wow, Intel at least gave ARM a few years before axing the divisions both times it tried to branch out. (The i960 and XScale were quite decent for their time and purpose.) One bad quarter and fledgling RISCV department is already cut down mercilessly.
Next up, the DGPU line, after finally delivering competitive midrange performance after many years of hard work and neglect. Can't let any non-x86 line see success.
Itanium was The Future for Intel and HP(/Compaq/DEC) at the time, along with a number of other companies that steadily lost faith. It was certainly not deliberately shit, the entire company was re-oriented around it while Netburst ran its course. Then the Itanic sunk, even if HP tried to bail it out for years, and nothing else has been "The Future" since then. (Although x86 itself has certainly seen many interesting new internal designs.)
I don't think DEC should be in that list of companies supporting Itanic. DEC had its Alpha CPUs (and also designed and manufactured StrongARM). I remember the Alpha CPU team writing papers explaining why Alpha was able to be higher performance that Itanic, and their arguments made a lot of sense. DEC stuck with Alpha until they went bankrupt. Oops.
My understanding is that DEC stuck with Alpha until they were bought by Compaq, and that if they had stuck with it AFTER that they would potentially have been in much better shape (same as SGI with MIPS).
In fact, it's interesting to consider that while Itanic didn't sink Intel, it DID sink some of their competitors.
It sounds like Pathfinder was a fairly low-key project at Intel - maybe just a couple of engineers working on it... Maybe they couldn't sustain it with the interest it was receiving, and needed more resources than Intel was prepared to give it?
Tom's Hardware reports that the HiFive Pro P550 (codenamed Horse Creek) platform is still going ahead (thankfully) : so I guess IFS is still hoping to attract RISC-V designs to fab..?
Given that Intel seem to be in financial freefall, I think SiFive was right to resist Intel's attempt to buy them out - there'd be nothing left of SiFive at this point.
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Extreme Tech were reporting that Intel were going to announce the use of an "entirely new microarchitecture" (in the announcement on the 26th)... I take it that didn't happen. I'd hoped they were going to put RISC-V at its heart.
I'd say they've got good reason to panic... whichever sector they look at they're getting beaten by the competition:
- it's widely acknowledged that they lost out to Arm big time in 2007, and with that IoT, smartphones, tablets, and now laptops and desktops
- AMD are using smaller nodes and creating better X86 CPUs and
- even the datacentre business is looking at Arm (and RISC-V has designs more powerful than Intel has to offer)
It's a good job that they've got a nationalist, protectionist government to look after them. :/
Worth remembering that Intel has many divisions and foci! It may be that Pathfinder was envisaged as a "group wide" entity, which has become a luxury they cannot afford, and so the RISC-V expertise has now devolved back to the individual divisions (e.g. the FPGA group f/k/a Altera, the not-wholly-owned SiFive, and so on).
I suspect more than a few vendors found that with the inevitably ill-fated Itanium (inevitably ill-fated to almost everyone on the outside anyway). The same hold true for providers of systems and services, there is always a risk.
It pays to put in some research though, as a vendor found when they boldly announced in a product release event that they were going to replace their click-once application with a future proof application built in Silverlight and I was unable not to laugh out loud at the stupidity (other than being a dumb tactical move, Silverlight had been announced as dead over six months earlier - it had been dead far longer than that of course). To their credit they did ask why I laughed, looked very concerned when I showed the EOL news and notices and went back to their office and made a very rapid change of strategy.
nearly-random policy, investment, and departmental/program changes. "New thing! It's on! No, it's off! We will! We won't! It's free! Some users will have to pay a fee! Fees are now per-CPU + x*number-of-threads + y*phase-of-the-moon! New new thing! ..."
Amateur! Your sales department will be having words... you omitted the key multiplier of the total number of staff in the organisation paying the fee... including contract cleaners, passing window cleaners, anybody who turns up in the staff car park to replace a windscreen and anybody who has ever applied to work for the organisation or even considered doing so.
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